Patents by Inventor Michael S. Shaffer
Michael S. Shaffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140280429Abstract: In one embodiment, a four-input, four-output bin adder is disclosed. The bin adder comprises a two-by-three, multi-stage, cascaded array of two-input, two-output adder circuits. Each of the bin-adder input signals comprises a numeric data value and an associated address, and the bin adder is adapted to add together (a.k.a. accumulate) the numeric values of only those inputs signals having addresses that are the same. In particular, the inputs and outputs of the two-input, two-output adder circuits are connected together in such a way that each input signal is compared to every other input signal, in a round-robin configuration. If the associated addresses match, then the input signals' numeric data values are added (i.e., accumulated) and output as a single signal comprising the sum of the numeric data values and the common address.Type: ApplicationFiled: August 13, 2013Publication date: September 18, 2014Applicant: LSI CorporationInventors: Joseph A. Manzella, Michael S. Shaffer, Won J. Yoon, David L. Cargille
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Patent number: 8270289Abstract: Methods and apparatus are provided for framing synchronization control for a framer/mapper/multiplexor (FMM) device with 1+1 and equipment protection. FMM device are disclosed that synchronize one or more internal signals by changing a phase of the one or more internal signals without changing a frequency of the one or more internal signals based on a desired phase at a destination of each of the one or more internal signals. A programmable synchronization signal may optionally be employed for the synchronization.Type: GrantFiled: February 27, 2009Date of Patent: September 18, 2012Assignee: LSI CorporationInventors: Cheng Gang Duan, Lin Hua, Michael S. Shaffer, Tao Wang, Qian G. Xu
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Patent number: 8249063Abstract: A communication device comprises a signal combiner, first storage elements, second storage elements and a controller. The signal combiner is configured to combine overhead information with additional information in forming a frame of a signal. The first storage elements are adapted to receive respective portions of a given block of the overhead information to be applied to the signal combiner, and the second storage elements are coupled between respective ones of the first storage elements and respective inputs of the signal combiner. The controller is operative to monitor a count of portions of the frame as the frame is formed by the signal combiner and to control loading of the portions of the given block of the overhead information into the second storage elements from the first storage elements responsive to the monitored count.Type: GrantFiled: June 30, 2009Date of Patent: August 21, 2012Assignee: LSI CorporationInventors: Cheng Gang Duan, Lin Hua, Ze Mian Huang, Michael S. Shaffer, Tao Wang
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Patent number: 8179807Abstract: Techniques are disclosed for in-band communication of alarm status information or other information between physical layer devices comprising a working device and a protection device in a network-based communication system. In one aspect, a protection receive signal is monitored in the protection device for the presence of alarm status information. The protection device encodes alarm status information extracted from the protection receive signal, and inserts the encoded alarm status information into one or more designated portions of a protection loop-back signal supplied from the protection device to the working device. The protection loop-back signal is monitored in the working device and the encoded alarm status information therein is decoded and utilized by the working device to initiate a protection switching operation.Type: GrantFiled: November 6, 2007Date of Patent: May 15, 2012Assignee: LSI CorporationInventors: Cheng Gang Duan, Lin Hua, Michael S. Shaffer
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Patent number: 8169918Abstract: An apparatus for monitoring of received information in a communication device comprises a first buffer having a plurality of storage elements adapted to store respective portions of the received information, a second buffer coupled to the first buffer and having a plurality of storage elements corresponding to respective ones of the storage elements of the first buffer, and controller circuitry coupled to the buffers and operative to detect a message sequence comprising a plurality of the portions of the received information. The second buffer stores a previously-detected message sequence loaded from the first buffer into the second buffer under control of the controller circuitry. The controller circuitry in detecting a current message sequence is configurable in at least first and second different monitoring modes each associated with a different message format. The monitoring mode of the controller circuitry may be adaptively configured based at least in part on a detected message sequence.Type: GrantFiled: June 30, 2009Date of Patent: May 1, 2012Assignee: LSI CorporationInventors: Cheng Gang Duan, Lin Hua, Ze Mian Huang, Michael S. Shaffer, Qian Gao Xu
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Patent number: 7944830Abstract: Methods and apparatus are provided for evaluating the throughput limit of a communication system, such as a network node or system. A throughput limit of a communication system is evaluated by receiving a request to allocate at least one connection of a given data type; obtaining an assigned weight for the at least one connection, wherein the assigned weight is based on the throughput limit and a processing limit indicating a throughput of the communication system for the given data type within a given time window; and determining whether to allocate the at least one connection of a given data type based on whether a sum of the assigned weights for each existing allocated connection for each data type exceeds the throughput limit. The assigned weight for a given data type can be subtracted from the sum upon receiving a request to de-allocate a connection.Type: GrantFiled: August 7, 2008Date of Patent: May 17, 2011Assignee: Agere Systems Inc.Inventors: Michael S. Shaffer, Jay P. Wilshire, Harold J. Wilson
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Patent number: 7940808Abstract: A communications system includes a physical layer device (PLD) and a logical link device (LLD), each having respective send and receive interfaces being substantially identical to define symmetrical interfaces for the system. Accordingly, design and manufacturing is simplified compared to conventional systems. In addition, advantages are also provided in terms of loopback capability and packaging options. The PLD comprises a PLD send interface including PLD parallel information outputs, and a PLD receive interface including PLD parallel information inputs. Similarly, the LLD comprises an LLD receive interface including LLD parallel information inputs, and an LLD send interface including LLD parallel information outputs. Parallel communications channels connect the PLD information outputs to respective LLD information inputs, and connect the LLD information outputs to respective PLD information inputs.Type: GrantFiled: December 30, 2008Date of Patent: May 10, 2011Assignee: Agere Systems Inc.Inventors: Michael S. Shaffer, Himanshu Mahendra Thaker, Charles Albert Webb, III, Lesley Jen-Yuan Wu
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Publication number: 20100329122Abstract: An apparatus for monitoring of received information in a communication device comprises a first buffer having a plurality of storage elements adapted to store respective portions of the received information, a second buffer coupled to the first buffer and having a plurality of storage elements corresponding to respective ones of the storage elements of the first buffer, and controller circuitry coupled to the buffers and operative to detect a message sequence comprising a plurality of the portions of the received information. The second buffer stores a previously-detected message sequence loaded from the first buffer into the second buffer under control of the controller circuitry. The controller circuitry in detecting a current message sequence is configurable in at least first and second different monitoring modes each associated with a different message format. The monitoring mode of the controller circuitry may be adaptively configured based at least in part on a detected message sequence.Type: ApplicationFiled: June 30, 2009Publication date: December 30, 2010Inventors: Cheng Gang Duan, Lin Hua, Ze Mian Huang, Michael S. Shaffer, Qian Gao Xu
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Publication number: 20100329673Abstract: A communication device comprises a signal combiner, first storage elements, second storage elements and a controller. The signal combiner is configured to combine overhead information with additional information in forming a frame of a signal. The first storage elements are adapted to receive respective portions of a given block of the overhead information to be applied to the signal combiner, and the second storage elements are coupled between respective ones of the first storage elements and respective inputs of the signal combiner. The controller is operative to monitor a count of portions of the frame as the frame is formed by the signal combiner and to control loading of the portions of the given block of the overhead information into the second storage elements from the first storage elements responsive to the monitored count.Type: ApplicationFiled: June 30, 2009Publication date: December 30, 2010Inventors: Cheng Gang Duan, Lin Hua, Ze Mian Huang, Michael S. Shaffer, Tao Wang
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Patent number: 7792132Abstract: In one embodiment, the present invention is a framer/mapper/multiplexor (FMM) device that can simultaneously (i) send protection copies of both its working incoming high-speed (e.g., STS-12) signal and incoming low-speed signals to a protection FMM device, and (ii) receive corresponding protection signals from the protection FMM device. Furthermore, the FMM device can select between working and protection signals at a switching level (e.g., STS-1) lower than the high-speed level, allowing for 1+1 APS/MSP protection and equipment protection at the board level, the device level, and at the STS-1 level. Yet further, four or more FMM devices can be configured so that all FMM devices can communicate with their corresponding protection FMM devices using a single, shared, 4-pin link (e.g., quad-OC-3 mode), and still select between working and protection signals at the switching level (e.g., STS-1).Type: GrantFiled: December 10, 2008Date of Patent: September 7, 2010Assignee: Agere Systems Inc.Inventors: Si Ruo Chen, Chenggang Duan, Lin Hua, Michael S. Shaffer, Qian Gao Xu
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Publication number: 20100221001Abstract: Methods and apparatus are provided for framing synchronization control for a framer/mapper/multiplexor (FMM) device with 1+1 and equipment protection. FMM device are disclosed that synchronize one or more internal signals by changing a phase of the one or more internal signals without changing a frequency of the one or more internal signals based on a desired phase at a destination of each of the one or more internal signals. A programmable synchronization signal may optionally be employed for the synchronization.Type: ApplicationFiled: February 27, 2009Publication date: September 2, 2010Inventors: Cheng Gang Duan, Lin Hua, Michael S. Shaffer, Tao Wang, Qian G. Xu
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Patent number: 7742493Abstract: In a communication system comprising a mapper or other type of physical layer device coupled to a link layer device, the physical layer device comprises payload extraction circuitry and payload insertion circuitry. The payload extraction circuitry is configured to extract a payload from an ingress synchronous transport signal received over an ingress link, and the payload insertion circuitry is configured to insert a payload received from the link layer device into an egress synchronous transport signal for transmission over an egress link. The payload extracted from the ingress synchronous transport signal is transmitted by the physical layer device to the link layer device over an output serial data line of a serial interface, and the payload inserted into the egress synchronous transport signal is received by the physical layer device from the link layer device over an input serial data line of the serial interface.Type: GrantFiled: August 16, 2007Date of Patent: June 22, 2010Assignee: Agere Systems Inc.Inventors: Cheng Gang Duan, Lin Hua, Michael S. Shaffer
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Publication number: 20100142948Abstract: In one embodiment, the present invention is a framer/mapper/multiplexor (FMM) device that can simultaneously (i) send protection copies of both its working incoming high-speed (e.g., STS-12) signal and incoming low-speed signals to a protection FMM device, and (ii) receive corresponding protection signals from the protection FMM device. Furthermore, the FMM device can select between working and protection signals at a switching level (e.g., STS-1) lower than the high-speed level, allowing for 1+1 APS/MSP protection and equipment protection at the board level, the device level, and at the STS-1 level. Yet further, four or more FMM devices can be configured so that all FMM devices can communicate with their corresponding protection FMM devices using a single, shared, 4-pin link (e.g., quad-OC-3 mode), and still select between working and protection signals at the switching level (e.g., STS-1).Type: ApplicationFiled: December 10, 2008Publication date: June 10, 2010Applicant: Agere Systems Inc.Inventors: Si Ruo Chen, Chenggang Duan, Lin Hua, Michael S. Shaffer, Qian Gao Xu
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Publication number: 20100034247Abstract: Methods and apparatus are provided for evaluating the throughput limit of a communication system, such as a network node or system. A throughput limit of a communication system is evaluated by receiving a request to allocate at least one connection of a given data type; obtaining an assigned weight for the at least one connection, wherein the assigned weight is based on the throughput limit and a processing limit indicating a throughput of the communication system for the given data type within a given time window; and determining whether to allocate the at least one connection of a given data type based on whether a sum of the assigned weights for each existing allocated connection for each data type exceeds the throughput limit. The assigned weight for a given data type can be subtracted from the sum upon receiving a request to de-allocate a connection.Type: ApplicationFiled: August 7, 2008Publication date: February 11, 2010Inventors: Michael S. Shaffer, Jay P. Wilshire, Harold J. Wilson
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Publication number: 20090196605Abstract: A communications system includes a physical layer device (PLD) and a logical link device (LLD), each having respective send and receive interfaces being substantially identical to define symmetrical interfaces for the system. Accordingly, design and manufacturing is simplified compared to conventional systems. In addition, advantages are also provided in terms of loopback capability and packaging options. The PLD comprises a PLD send interface including PLD parallel information outputs, and a PLD receive interface including PLD parallel information inputs. Similarly, the LLD comprises an LLD receive interface including LLD parallel information inputs, and an LLD send interface including LLD parallel information outputs. Parallel communications channels connect the PLD information outputs to respective LLD information inputs, and connect the LLD information outputs to respective PLD information inputs.Type: ApplicationFiled: December 30, 2008Publication date: August 6, 2009Applicant: AGERE SYSTEMS INC.Inventors: Michael S. Shaffer, Himanshu Mahendra Thaker, Charles Albert Webb, III, Lesley Jen-Yuan Wu
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Publication number: 20090115596Abstract: Techniques are disclosed for in-band communication of alarm status information or other information between physical layer devices comprising a working device and a protection device in a network-based communication system. In one aspect, a protection receive signal is monitored in the protection device for the presence of alarm status information. The protection device encodes alarm status information extracted from the protection receive signal, and inserts the encoded alarm status information into one or more designated portions of a protection loop-back signal supplied from the protection device to the working device. The protection loop-back signal is monitored in the working device and the encoded alarm status information therein is decoded and utilized by the working device to initiate a protection switching operation.Type: ApplicationFiled: November 6, 2007Publication date: May 7, 2009Inventors: Cheng Gang Duan, Lin Hua, Michael S. Shaffer
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Publication number: 20090046741Abstract: In a communication system comprising a mapper or other type of physical layer device coupled to a link layer device, the physical layer device comprises payload extraction circuitry and payload insertion circuitry. The payload extraction circuitry is configured to extract a payload from an ingress synchronous transport signal received over an ingress link, and the payload insertion circuitry is configured to insert a payload received from the link layer device into an egress synchronous transport signal for transmission over an egress link. The payload extracted from the ingress synchronous transport signal is transmitted by the physical layer device to the link layer device over an output serial data line of a serial interface, and the payload inserted into the egress synchronous transport signal is received by the physical layer device from the link layer device over an input serial data line of the serial interface.Type: ApplicationFiled: August 16, 2007Publication date: February 19, 2009Inventors: Cheng Gang Duan, Lin Hua, Michael S. Shaffer
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Patent number: 7486703Abstract: A communications system includes a physical layer device (PLD) and a logical link device (LLD), each having respective send and receive interfaces being substantially identical to define symmetrical interfaces for the system. Accordingly, design and manufacturing is simplified compared to conventional systems. In addition, advantages are also provided in terms of loopback capability and packaging options. The PLD comprises a PLD send interface including PLD parallel information outputs, and a PLD receive interface including PLD parallel information inputs. Similarly, the LLD comprises an LLD receive interface including LLD parallel information inputs, and an LLD send interface including LLD parallel information outputs. Parallel communications channels connect the PLD information outputs to respective LLD information inputs, and connect the LLD information outputs to respective PLD information inputs.Type: GrantFiled: July 27, 2004Date of Patent: February 3, 2009Assignee: Agere Systems Inc.Inventors: Michael S. Shaffer, Himanshu Mahendra Thaker, Charles Albert Webb, III, Lesley Jen-Yuan Wu
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Patent number: 6909727Abstract: A communications system comprises a physical layer device (PLD) including a PLD send interface which, in turn, includes PLD parallel information outputs and at least one PLD control output. The system also includes a logical link device (LLD) which comprises an LLD receive interface which, in turn, includes LLD parallel information inputs and at least one LLD control input. First parallel communications channels connect the PLD information outputs to respective LLD information inputs, and at least one second communications channel connects the at least one PLD control output to the at least one LLD control input so that control signals are sent from the PLD to the LLD out-of-band from information signals. Accordingly, control speed is enhanced, and information throughput efficiency is not compromised.Type: GrantFiled: December 13, 1999Date of Patent: June 21, 2005Assignee: Agere Systems Inc.Inventors: Michael S. Shaffer, Himanshu Mahendra Thaker, Charles Albert Webb, III, Lesley Jen-Yuan Wu
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Publication number: 20040264496Abstract: A communications system includes a physical layer device (PLD) and a logical link device (LLD), each having respective send and receive interfaces being substantially identical to define symmetrical interfaces for the system. Accordingly, design and manufacturing is simplified compared to conventional systems. In addition, advantages are also provided in terms of loopback capability and packaging options. The PLD comprises a PLD send interface including PLD parallel information outputs, and a PLD receive interface including PLD parallel information inputs. Similarly, the LLD comprises an LLD receive interface including LLD parallel information inputs, and an LLD send interface including LLD parallel information outputs. Parallel communications channels connect the PLD information outputs to respective LLD information inputs, and connect the LLD information outputs to respective PLD information inputs.Type: ApplicationFiled: July 27, 2004Publication date: December 30, 2004Inventors: Michael S. Shaffer, Himanshu Mahendra Thaker, Charles Albert Webb, Lesley Jen-Yuan Wu