Abstract: A system for testing and calibrating communications equipment or modules. A processor is configured to perform a test or calibration procedure on a communications unit under test (UUT) in response to commands entered by an operator. Test and measurement instruments arranged to be responsive to the computer include a power supply for activating selected portions of signal paths in the UUT, one or more signal generators, and one or more instruments for measuring output signals produced by the UUT in response to the test signals. The UUT has switches and terminals for inputting test signals from and returning output signals to the instruments, and an adapter is connected between the processor and the UUT. When performing a calibration procedure, the adapter operates the switches and connects the terminals on the UUT to the test and measurement instruments under the control of the processor.

Abstract: A communications radio has an IF stage with an associated filter array. The array includes at least one narrowband filter whose passband is less than 3 MHz, at least one wideband filter whose passband is 3 MHz or greater, a first switch with a common pole connected to an input terminal of the array, a second switch with a common pole connected to an output terminal of the array, a third switch whose common pole is operatively connected to the input terminal, and a fourth switch whose common pole is operatively connected to the output terminal. The first and the second switches cooperate to insert a selected filter between the first and second terminals. The third and the fourth switches cooperate to insert the filter array into either a receive signal path when the radio is in a receive mode, or a transmit signal path when in a transmit mode.

Abstract: A compact radio core engine (CE) module uniquely small in size and power consumption, in which only two circuit boards provide all the modem and transceiver functions needed for modern military radios. A modem circuit board has modem devices and a first connector mounted on the board, and a radio frequency (RF) circuit board has RF devices and a second connector mounted on the board. A module frame has an interior wall, and a side wall about the periphery of the interior wall. The modem and the RF circuit boards are positioned on opposite sides of the interior wall, and the connectors on the two boards mate with one another through an opening in the interior wall to exchange operating data and signals between the devices on the boards. The modem circuit board is seated entirely within a recess formed by the interior and the side walls of the frame.

Abstract: A method and apparatus of minimizing corruption of a reference clock to a RF circuitry in a radio system is disclosed. A DICE-T receives a reference clock in a Low Voltage Differential Signal (LVDS) format from a GVA. The DICE-T personality card converts the reference clock signal into an analog signal. The analog signal is supplied to the Core Engine RF card and the LVDS format signal is supplied to the Core Engine modem for local clocking. The Core Engine RF feeds the analog signal into a programmable phase locked loop chip to generate all the clocks required for RF processing. The analog signal is also used to provide the clocks to the ADC and DAC of core engine modem. By routing the reference clock directly to the RF card then deriving the modem clocks, the phase noise of the reference clock is reduced.

Abstract: A communications radio or transceiver having an extended upper operating frequency limit of at least 6 GHz. The radio includes a first IF conversion stage for receiving and downconverting a RF input signal to a first IF signal, and a second IF conversion stage for downconverting the first IF signal to a second IF signal. The first and the second conversion stages each have adjustable first and second attenuators, a serial peripheral interface (SPI) for controlling the attenuators in response to command words, a mixer coupled to an output of the second attenuator, and a buffer for applying a local oscillator (LO) signal to an input of the mixer. Each conversion stage is in the form of an integrated circuit chip. Component devices of each chip and electrical connections between the components, are dimensioned so that the chip has a 6 GHz upper frequency limit.

Abstract: A filter package for communications equipment includes two or more filters in die form, each having a different frequency response. A first switch and a second switch are operatively connected to the filters and are configured to select a desired filter for operation in a signal stage of the equipment. The filters are aligned and stacked one over the other in the form of a package having an input terminal that is tied to a common terminal of the first switch, and an output terminal tied to a common terminal of the second switch. When the input and the output terminals of the filter package are connected to corresponding terminals of an intermediate frequency (IF) stage in a communications transceiver, the package can support both narrowband and wideband waveforms defined by the Joint Tactical Radio System (JTRS).

Abstract: A method of controlling the phases of RF output signals from a number of radio transmitters. A given radio has at least one synthesizer as a source of its RF output signal, and the synthesizer produces an output the phase offset of which relative to a reference signal is controlled by a phase offset command. A path from an antenna port of the radio obtains a fed back RF output signal and a phase difference between the reference signal and the fed back RF output signal is measured. A value of a zero degree phase offset command for the synthesizer is determined such that the phase difference between the reference signal and the fed back RF signal is nominally zero, and the value is stored. A phase offset command for providing a desired phase offset for the RF output signal is then determined based the stored value of the zero degree phase offset command.

Abstract: A communications radio has an IF stage with an associated filter array. The array includes at least one narrowband filter whose passband is less than 3 MHz, at least one wideband filter whose passband is 3 MHz or greater, a first switch with a common pole connected to an input terminal of the array, a second switch with a common pole connected to an output terminal of the array, a third switch whose common pole is operatively connected to the input terminal, and a fourth switch whose common pole is operatively connected to the output terminal. The first and the second switches cooperate to insert a selected filter between the first and second terminals. The third and the fourth switches cooperate to insert the filter array into either a receive signal path when the radio is in a receive mode, or a transmit signal path when in a transmit mode.

Abstract: A compact communications radio core engine (CE) module includes a modem circuit board having a first connector, and a radio frequency (RF) circuit board having a second connector configured to mate with the first connector of the modem circuit card. A module shell is constructed and arranged to contain the modem and the RF circuit boards in such an orientation so that the second connector of the RF circuit board can operatively engage the first connector of the modem circuit card.

Abstract: A communications radio or transceiver having an extended upper operating frequency limit of at least 6 GHz. The radio includes a first IF conversion stage for receiving and downconverting a RF input signal to a first IF signal, and a second IF conversion stage for downconverting the first IF signal to a second IF signal. The first and the second conversion stages each have adjustable first and second attenuators, a serial peripheral interface (SPI) for controlling the attenuators in response to command words, a mixer coupled to an output of the second attenuator, and a buffer for applying a local oscillator (LO) signal to an input of the mixer. Each conversion stage is in the form of an integrated circuit chip. Component devices of each chip and electrical connections between the components, are dimensioned so that the chip has a 6 GHz upper frequency limit.

Abstract: A system for testing and calibrating communications equipment or modules. A processor is configured to perform a test or calibration procedure on a communications unit under test (UUT) in response to commands entered by an operator. Test and measurement instruments arranged to be responsive to the computer include a power supply for activating selected portions of signal paths in the UUT, one or more signal generators, and one or more instruments for measuring output signals produced by the UUT in response to the test signals. The UUT has switches and terminals for inputting test signals from and returning output signals to the instruments, and an adapter is connected between the processor and the UUT. When performing a calibration procedure, the adapter operates the switches and connects the terminals on the UUT to the test and measurement instruments under the control of the processor.

Abstract: A method of controlling the phases of RF output signals from a number of radio transmitters. A given radio has at least one synthesizer as a source of its RF output signal, and the synthesizer produces an output the phase offset of which relative to a reference signal is controlled by a phase offset command. A path from an antenna port of the radio obtains a fed back RF output signal and a phase difference between the reference signal and the fed back RF output signal is measured. A value of a zero degree phase offset command for the synthesizer is determined such that the phase difference between the reference signal and the fed back RF signal is nominally zero, and the value is stored. A phase offset command for providing a desired phase offset for the RF output signal is then determined based the stored value of the zero degree phase offset command.

Abstract: A method and apparatus of minimizing corruption of a reference clock to a RF circuitry in a radio system is disclosed. A DICE-T receives a reference clock in a Low Voltage Differential Signal (LVDS) format from a GVA. The DICE-T personality card converts the reference clock signal into an analog signal. The analog signal is supplied to the Core Engine RF card and the LVDS format signal is supplied to the Core Engine modem for local clocking. The Core Engine RF feeds the analog signal into a programmable phase locked loop chip to generate all the clocks required for RF processing. The analog signal is also used to provide the clocks to the ADC and DAC of core engine modem. By routing the reference clock directly to the RF card then deriving the modem clocks, the phase noise of the reference clock is reduced.

Abstract: A filter package for communications equipment includes two or more filters in die form, each having a different frequency response. A first switch and a second switch are operatively connected to the filters and are configured to select a desired filter for operation in a signal stage of the equipment. The filters are aligned and stacked one over the other in the form of a package having an input terminal that is tied to a common terminal of the first switch, and an output terminal tied to a common terminal of the second switch. When the input and the output terminals of the filter package are connected to corresponding terminals of an intermediate frequency (IF) stage in a communications transceiver, the package can support both narrowband and wideband waveforms defined by the Joint Tactical Radio System (JTRS).