Patents by Inventor Michael S. Yang

Michael S. Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250084056
    Abstract: Disclosed are compounds of Formula (I): or stereoisomers, tautomers, or salts thereof, wherein: R is and Ring A, L, R1, R2, R3, m, and n are defined herein. Also disclosed are methods of using such compounds to decrease the level Cyclin E1; and pharmaceutical compositions comprising such compounds. These compounds are useful in the treatment of proliferative disorders, such as cancer.
    Type: Application
    Filed: September 12, 2024
    Publication date: March 13, 2025
    Applicant: BRISTOL-MYERS SQUIBB COMPANY
    Inventors: DANIEL FERRANTE, ZHONGHUI LU, PETER KINAM PARK, JOHN S. TOKARSKI, VIPIN YADAV, MICHAEL G. YANG, JINYI ZHU, ANDREW P. DEGNAN, JAMES KEMPSON, RICHARD CHARLES BURRELL
  • Patent number: 9886396
    Abstract: In one embodiment, a processor includes a frontend unit having an instruction decoder to receive and to decode instructions of a plurality of threads, an execution unit coupled to the instruction decoder to receive and execute the decoded instructions, and an instruction retirement unit having a retirement logic to receive the instructions from the execution unit and to retire the instructions associated with one or more of the threads that have an instruction or an event pending to be retired. The instruction retirement unit includes a thread arbitration logic to select one of the threads at a time and to dispatch the selected thread to the retirement logic for retirement processing.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: February 6, 2018
    Assignee: Intel Corporation
    Inventors: Roger Gramunt, Rammohan Padmanabhan, Ramon Matas, Neal S. Moyer, Benjamin C. Chaffin, Avinash Sodani, Alexey P. Suprun, Vikram S. Sundaram, Chung-Lun Chan, Gerardo A. Fernandez, Julio Gago, Michael S. Yang, Aditya Kesiraju
  • Publication number: 20160179533
    Abstract: In one embodiment, a processor includes a frontend unit having an instruction decoder to receive and to decode instructions of a plurality of threads, an execution unit coupled to the instruction decoder to receive and execute the decoded instructions, and an instruction retirement unit having a retirement logic to receive the instructions from the execution unit and to retire the instructions associated with one or more of the threads that have an instruction or an event pending to be retired. The instruction retirement unit includes a thread arbitration logic to select one of the threads at a time and to dispatch the selected thread to the retirement logic for retirement processing.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Inventors: Roger Gramunt, Rammohan Padmanabhan, Ramon Matas, Neal S. Moyer, Benjamin C. Chaffin, Avinash Sodani, Alexey P. Suprun, Vikram S. Sundaram, Chung-Lun Chan, Gerardo A. Fernandez, Julio Gago, Michael S. Yang, Aditya Kesiraju
  • Patent number: 7633193
    Abstract: A cooling system for an electrical motor or generator includes a first cooling loop, a second cooling loop, and a heat exchange system. The first cooling loop may extract heat from an iron stack and winding of the electrical motor or generator. The second cooling loop may extract heat from end turns of the stator winding, the rotor, and the bearings independently from and simultaneously to the first cooling loop. At least the first cooling loop may pass through the heat exchange system. A liquid coolant may circulate in the first cooling loop and a compressed gas, such as compressed air or compressed refrigerant in vapor form, may circulate in the second cooling loop. The cooling system and method for an electrical motor or generator may be suitable for, but not limited to, applications in the aircraft and aerospace industries, such as driving a cabin air compressor of an aircraft.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: December 15, 2009
    Assignee: Honeywell International Inc.
    Inventors: Mike M. Masoudipour, Jeff A. Lotterman, Carol A. Oximberg, Michael S. Yang
  • Publication number: 20080168796
    Abstract: A cooling system for an electrical motor or generator includes a first cooling loop, a second cooling loop, and a heat exchange system. The first cooling loop may extract heat from an iron stack and winding of the electrical motor or generator. The second cooling loop may extract heat from end turns of the stator winding, the rotor, and the bearings independently from and simultaneously to the first cooling loop. At least the first cooling loop may pass through the heat exchange system. A liquid coolant may circulate in the first cooling loop and a compressed gas, such as compressed air or compressed refrigerant in vapor form, may circulate in the second cooling loop. The cooling system and method for an electrical motor or generator may be suitable for, but not limited to, applications in the aircraft and aerospace industries, such as driving a cabin air compressor of an aircraft.
    Type: Application
    Filed: January 17, 2007
    Publication date: July 17, 2008
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: MIKE M. MASOUDIPOUR, JEFF A. LOTTERMAN, CAROL A. OXIMBERG, MICHAEL S. YANG
  • Patent number: 5465331
    Abstract: A parallel, scalable internetworking unit (IU) architecture employing at least two network controllers (NCs), a foreground buffer controller with local memory, a background buffer controller with local memory, a node processor (NP) and a buffer memory. Each network attached to the IU has an individual network controller which communicates with the foreground buffer controller. The foreground buffer controller interfaces with NCs and maintains queueing information. The background buffer controller communicates with the foreground buffer controller for maintaining packets of data as linked lists of buffers in the buffer memory. The NP communicates with both the foreground and background buffer controllers to process stored header information. And, a connection matrix is provided to dynamically interconnect multiple IUs for increased parallel processing of packet traffic and processing.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: November 7, 1995
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Yang, Jih-Shyr Yih