Abstract: A memory system having a plurality of memory cells for storing payload data and redundancy data. The memory system having a read-out circuit configured to read-out a status of the plurality of memory cells, the read-out status having payload data, redundancy data and associated reliability information. Moreover, the memory system has a data processor configured to derive the payload data from the read-out status using the reliability information.

Abstract: A memory system having a plurality of memory cells for storing payload data and redundancy data. The memory system having a read-out circuit configured to read-out a status of the plurality of memory cells, the read-out status having payload data, redundancy data and associated reliability information. Moreover, the memory system has a data processor configured to derive the payload data from the read-out status using the reliability information.

Abstract: A memory system having a plurality of memory cells for storing payload data and redundancy data. The memory system having a read-out circuit configured to read-out a status of the plurality of memory cells, the read-out status having payload data, redundancy data and associated reliability information. Moreover, the memory system has a data processor configured to derive the payload data from the read-out status using the reliability information.

Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a memory cell block having a plurality of memory cells, a storage portion configured to store information about a quality characteristic of the memory cells of the memory cell block, and a controller configured to control a read operation, and to change the information about the quality characteristic depending on a quality of a read operation.

Abstract: An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

Abstract: An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a memory cell block having a plurality of memory cells, a storage portion configured to store information about a quality characteristic of the memory cells of the memory cell block, and a controller configured to control a read operation, and to change the information about the quality characteristic depending on a quality of a read operation.

Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, at least one error detection circuit, and a controller configured to control a read operation to read state information from the at least one memory cell by reading a memory cell state information bypassing the at least one error correction circuit, or by reading the memory cell state information and supplying it to the at least one error correction circuit.

Abstract: A memory system having a plurality of memory cells for storing payload data and redundancy data. The memory system having a read-out circuit configured to read-out a status of the plurality of memory cells, the read-out status having payload data, redundancy data and associated reliability information. Moreover, the memory system has a data processor configured to derive the payload data from the read-out status using the reliability information.

Abstract: A circuit arrangement for supplying configuration data in an FPGA device includes a plurality of output flip flops allocated to respective configurable logic cells of the FGPGA device. Each output flip flop comprises at least one data input and one data output and a data input of a first output flip flop of the plurality of output flip flops is switchably connected to a data output of a second output flip flop of the plurality of output flip flops for forming a shift register by means of a switching device integrated in the FPGA device.

Abstract: A mask-programmable logic macro includes at least three input terminals an output terminal and a first set of transistors comprised of at least three transistors formed on a semiconductor substrate, each of the transistors comprising a controllable path and a control terminal. The controllable paths can be connected in series with one another between a first supply terminal and the output terminal by metallizing first metallization regions. The the transistors of the first set of transistors are arranged on the semiconductor substrate in such a way that at least one controllable path of the transistors can be bridged by metallizing one of the first metallization regions. A respective of the input terminals can be connected to a respective of the control terminals by metallizing a second metallization region.

Abstract: A configurable logic component (30) does not have a local configuration memory. The configuration of the configurable logic component is defined by applied voltages. The configuration voltages are advantageously generated in an external configuration memory (2). In one preferred refinement, a memory chip (20) (for example EEPROM) and the inventive logic component without a configuration memory (30) are mounted face-to-face. An intermediate, structured solder layer (40) makes available a plurality of electrical connections.

Abstract: A read out device for reading out a data word from a memory cell is described. The read out device has memory cells, inputs for input variables for selecting a memory cell and a hierarchical arrangement of multiplexers having N hierarchical levels. The control inputs of the multiplexers of a hierarchical level are connected to an input, the inputs of the hierarchical arrangement of multiplexers are connected to the outputs of the memory cells and the number of memory cells is less than 2N.

Abstract: A logic circuit arrangement including at least two data signal inputs, at which at least two data signals are provided, a first signal path coupled to the data signal inputs, and having a plurality of transistors of a first conduction type, and a plurality of control inputs coupled to the transistors.

Abstract: A mask-programmable logic macro includes at least three input terminals an output terminal and a first set of transistors comprised of at least three transistors formed on a semiconductor substrate, each of the transistors comprising a controllable path and a control terminal. The controllable paths can be connected in series with one another between a first supply terminal and the output terminal by metallizing first metallization regions. The the transistors of the first set of transistors are arranged on the semiconductor substrate in such a way that at least one controllable path of the transistors can be bridged by metallizing one of the first metallization regions. A respective of the input terminals can be connected to a respective of the control terminals by metallizing a second metallization region.

Abstract: A circuit arrangement for supplying configuration data in an FPGA device includes a plurality of output flip flops allocated to respective configurable logic cells of the FGPGA device. Each output flip flop comprises at least one data input and one data output and a data input of a first output flip flop of the plurality of output flip flops is switchably connected to a data output of a second output flip flop of the plurality of output flip flops for forming a shift register by means of a switching device integrated in the FPGA device.

Abstract: An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

Abstract: A configurable logic component (30) does not have a local configuration memory. The configuration of the configurable logic component is defined by applied voltages. The configuration voltages are advantageously generated in an external configuration memory (2). In one preferred refinement, a memory chip (20) (for example EEPROM) and the inventive logic component without a configuration memory (30) are mounted face-to-face. An intermediate, structured solder layer (40) makes available a plurality of electrical connections.

Abstract: A read out device for reading out a data word from a memory cell is described. The read out device has memory cells, inputs for input variables for selecting a memory cell and a hierarchical arrangement of multiplexers having N hierarchical levels. The control inputs of the multiplexers of a hierarchical level are connected to an input, the inputs of the hierarchical arrangement of multiplexers are connected to the outputs of the memory cells and the number of memory cells is less than 2N.

Abstract: A logic circuit arrangement contains at least two data signal inputs, at which at least two data signals can be provided, and contains a first signal path having a plurality of transistors of a first conduction type, said signal path being coupled to the data signal inputs. The logic circuit arrangement furthermore contains a plurality of control inputs coupled to the transistors.