Abstract: A system for testing semiconductor devices is disclosed. In one embodiment, the test system being configured to be electrically connected via parallel wiring paths to a plurality of contact pins of a number of devices under test. The test system having at least one signal distribution matrix arranged in the wiring path to provide signals for testing and/or power supply to the devices.

Abstract: The invention provides a method for testing circuit units to be tested in a test apparatus, different identification units being assigned to the circuit units to be tested, the circuit units to be tested being connected to the test apparatus, a tester data stream including command blocks being output from the test apparatus, the tester data stream being compared with the identification units, the circuit unit to be tested, the identification unit of which matches the tester data stream output by the test apparatus, being activated and at least one command block for this circuit unit to be tested being processed in the circuit unit to be tested, whereupon the circuit unit to be tested is deactivated.

Abstract: A semiconductor device test method for testing a semiconductor device is disclosed. In one embodiment, for transmitting control information to a device that is connected between a test device and the semiconductor device, a non-standard-compliant signal is sent to the device. Furthermore, the invention relates to a semiconductor device test device and a device that is, for performing a semiconductor device test method, connected between a test device and a semiconductor device to be tested.

Abstract: The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.

Abstract: Test circuit for testing a synchronous memory circuit having a frequency multiplication circuit which multiplies a clock frequency of a low-frequency clock signal received from an external test unit by a particular frequency multiplication factor a test data generator which produces test data on the basis of data control signals received from the external test unit and outputs them to a data output driver a first signal delay circuit for delaying the test data which are output by the test data generator by an adjustable first delay time, a second signal delay circuit for delaying data which are read out of the synchronous memory circuit and are received by a data input driver in the test circuit by an adjustable second delay time, and having a data comparison circuit which compares the test data produced by the test data generator with the data read out of the memory circuit and, on the basis of the comparison result, outputs an indicator signal to the external test unit which indicates whether the synchronou

Abstract: A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device and circuit under test. The chip has a switching/detection unit that tests the chip based on external criteria between a first normal operating mode in which the chip tests the circuit to be tested, and a second operating mode in which programmable registers of the register unit of a receiver of the chip are programmed by the external test device. The registers store constants and variables for generating the test signals and for evaluating them. The chip generates test signals and transceiver for sending the test signals and receiving response signals generated thereby.

Abstract: An address generator is provided for generating addresses for testing an addressable circuit. The address generator can include a base address register for buffer-storing a base address. The base address register can be assigned an associated offset register group having a plurality of offset registers for buffer-storing relative address values. Further, the address generator can include a first multiplexer circuit which is dependent on a base register selection control signal, switches through an address buffer-stored in the base address register to a first input of an addition circuit and to an address bus, which is connected to the circuit to be tested. A second multiplexer circuit can be dependent on the base register selection control signal, through-connects the offset register group associated with the through-connected base address register to a third multiplexer circuit, which is dependent on an offset register selection control signal.

Abstract: The invention provides a method for testing circuit units to be tested in a test apparatus, different identification units being assigned to the circuit units to be tested, the circuit units to be tested being connected to the test apparatus, a tester data stream including command blocks being output from the test apparatus, the tester data stream being compared with the identification units, the circuit unit to be tested, the identification unit of which matches the tester data stream output by the test apparatus, being activated and at least one command block for this circuit unit to be tested being processed in the circuit unit to be tested, whereupon the circuit unit to be tested is deactivated.

Abstract: The invention provides a method for testing wafers (101) to be tested in a test device (100), in which the test device (100) can be calibrated, at least one calibration wafer (102) being automatically introduced into the test device (100) by means of a handling unit (103), calibration values of the test device (100) being determined by means of a control by a calibration sequence control unit (105), the calibration values determined being stored in a memory unit (106), the test device (100) being calibrated by means of the stored calibration values, the calibration wafer (102) being output from the calibrated test device (100), and at least one wafer (101) to be tested being introduced into the calibrated test device (100) by means of the handling unit (103) and being tested by a control by means of a test sequence control unit (104) in the calibrated test device (100), the stored calibration values being applied.

Abstract: A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.

Abstract: Test data generator for generating test data patterns for the testing of a circuit having a frequency multiplication circuit, which increases a low clock frequency of an input clock signal received by a test unit with a specific clock frequency multiplication factor. Also provided is a plurality of data registers for storing test data words read from the data registers, and multiplexer that switches through a test data word read from a data register with the high clock frequency of the output clock signal to a data bus in a way dependent on a register selection control datum of a multi-position register selection control data vector.

Abstract: The novel address counter can be used in combination with an existing test unit—serving for testing digital circuits—for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable offset registers, with a multiplexer circuit and a selection and combination circuit, on the basis of input signals which are fed in at low frequency and in parallel by the test unit. Simple address changes and address jumps can be realized at a high clock frequency in a very flexible manner.

Abstract: A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.

Abstract: A test circuit is adapted to test circuits having a high-frequency clock signal. The test circuit is positioned between a conventional tester and the circuit to be tested. The test circuit includes a frequency multiplication circuit which multiplies the clock signal of the conventional tester to produce a high-frequency clock signal. The test circuit also receives control signals from the conventional tester. The control signals are output to the circuit to be tested via a bus.

Abstract: In order to calibrate a test system for semiconductor components, use is made of a test substrate which has connecting contact points that are associated with one another in pairs. The contact points of the pairs are disposed at different distances from one another and they are connected by conductor tracks of approximately the same length. As a result, equalization of all the signal paths is achieved. In each case, a probe belonging to a probe card or a reference probe is placed onto the connecting contact points of a pair, so that the test system can be calibrated as far as a respective connecting contact of a component.

Abstract: The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.

Abstract: Test circuit for testing a circuit to be tested, having a test data generator, which generates test data in a manner dependent on data control signals which are received via data control lines from an external test unit, a data output driver for outputting the generated test data via data line pairs of a differential data bus to the circuit to be tested, a data input circuit for receiving data that are read from the circuit to be tested and transmitted via the data line pairs of the differential data bus, a data comparison circuit, which compares the generated data and the read-out data and, in a manner depend at on the comparison result transmits an indication signal, which indicates whether the circuit to be tested is functional, to the external test unit via an indication signal line.

Abstract: The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.

Abstract: The invention provides a method for testing wafers (101) to be tested in a test device (100), in which the test device (100) can be calibrated, at least one calibration wafer (102) being automatically introduced into the test device (100) by means of a handling unit (103), calibration values of the test device (100) being determined by means of a control by a calibration sequence control unit (105), the calibration values determined being stored in a memory unit (106), the test device (100) being calibrated by means of the stored calibration values, the calibration wafer (102) being output from the calibrated test device (100), and at least one wafer (101) to be tested being introduced into the calibrated test device (100) by means of the handling unit (103) and being tested by a control by means of a test sequence control unit (104) in the calibrated test device (100), the stored calibration values being applied.

Abstract: An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.