Abstract: The invention is a system and method for reconfigurable computers. The invention involves a plurality of reconfigurable component clusters (RCCs), each of which can change their respective configuration upon receiving a configuration command. The invention uses a reconfiguration network for distributing the configuration command to the RCCs, wherein the reconfiguration network comprises a plurality of cells, wherein each RCC is connected to a cell.

Abstract: A method of designing a custom circuit device begins with a high level architecture of subsystems coupled by virtual wires. The method comprises first through third steps. The first step comprises spatially placing the subsystems onto tiles. The second step comprises routing the virtual wires that cross boundaries of the tiles onto an interconnect architecture. The interconnect architecture comprises switches and registers. Some of the switches route a signal from a first subsystem located on a first tile to a second subsystem located on a second tile. At least two of the registers consecutively latch the signal at a time interval of no more than a repeating time period. The third step comprises scheduling of tasks according to clock cycles. According to an embodiment of the method, the repeating time period comprises a clock cycle period. According to another embodiment of the method, the repeating time period comprises a multiple of the clock cycle period.

Abstract: A reconfigurable memory system includes processors and memory modules. A reconfiguration system is operable to reconfigure the memory system into multiple configurations. In each configuration, one or more memory modules are provisioned for each processor.

Abstract: A system installer is operable to configure hardware components in a reconfigurable data center for a hardware platform. The system installer is also operable to install software on the hardware platform.

Abstract: A description of components in a reconfigurable data center is received. A set of components from the description is selected for a physical platform based on a logical platform specification.

Abstract: A service configuration for a service is generated using a service specification and at least one library including at least one of a hardware component and a software component available to be implemented for the service.

Abstract: A reconfigurable device comprises tiles and an interconnect architecture. Each of the tiles comprises a circuit. The interconnect architecture couples to the circuit of each tile and comprises switches and registers. In operation some of the switches route a signal from a first tile to a second tile along the interconnect architecture and at least two of the registers consecutively latch the signal at a time interval of no more than a repeating time period. In one embodiment of the reconfigurable device, the repeating time period comprises a clock cycle period. In another embodiment of the reconfigurable device, the repeating time period comprises a multiple of the clock cycle period.

Abstract: A method of designing a custom circuit device begins with a high level architecture of subsystems coupled by virtual wires. The method comprises first through third steps. The first step comprises spatially placing the subsystems onto tiles. The second step comprises routing the virtual wires that cross boundaries of the tiles onto an interconnect architecture. The interconnect architecture comprises switches and registers. Some of the switches route a signal from a first subsystem located on a first tile to a second subsystem located on a second tile. At least two of the registers consecutively latch the signal at a time interval of no more than a repeating time period. The third step comprises scheduling of tasks according to clock cycles. According to an embodiment of the method, the repeating time period comprises a clock cycle period. According to another embodiment of the method, the repeating time period comprises a multiple of the clock cycle period.

Abstract: A branch operation is processed using a branch predict instruction and an associated branch instruction. The branch predict instruction indicates a predicted direction, a target address, and an instruction address for the associated branch instruction. When the branch predict instruction is detected, the target address is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address. The branch predict instruction may also include hint information for managing the storage and use of the branch prediction information.

Abstract: A branch operation is processed using a branch predict instruction and an associated branch instruction. The branch predict instruction indicates a predicted direction, a target address, and an instruction address for the associated branch instruction. When the branch predict instruction is detected, the target address is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address. The branch predict instruction may also include hint information for managing the storage and use of the branch prediction information.

Abstract: A computer system provides fast evaluation of predicates and Boolean expressions with a set of operations for determining a value in a specified register from a plurality of inputs. The execution of each operation is defined by two functions of the operation's inputs: a result function which yields a result value, and an enable function which determines whether the result value is written to the specified register. To evaluate a Boolean expression with the operations, the register is preset to a Boolean value, e.g. one for an AND reduction, zero for an OR reduction. The operations can then write a Boolean value, e.g. zero for an AND reduction, one for an OR reduction, to the register if each operation's enable function evaluates true. The register then stores the correct value of the expression. The expression's value can be used as predicates to conditionally execute operations in a program.

Abstract: A processor and method that reduces instruction fetch penalty in the execution of a program sequence of instructions comprises a branch predict instruction that is inserted into the program at a location which precedes the branch. The branch predict instruction has an opcode that specifies a branch as likely to be taken or not taken, and which also specifies a target address of the branch. A block of target instructions, starting at the target address, is prefetched into the instruction cache of the processor so that the instructions are available for execution prior to the point in the program where the branch is encountered. Also specified by the opcode is an indication of the size of the block of target instructions, and a trace vector of a path in the program sequence that leads to the target from the branch predict instruction for better utilization of limited memory bandwidth.

Abstract: A process for optimizing compiler intermediate representation (IR) code, and data structures for implementing the process; the process is preferably embodied in a compiler computer program operating on an electronic computer or data processor with access to a memory storage means such as a random access memory and access to a program mass storage means such as an electronic magnetic disk storage device. The compiler program reads an input source program stored in the program mass storage means and creates a dynamic single assignment intermediate representation of the source program in the memory using pseudo-machine instructions. To create the dynamic single assignment intermediate representation, during compilation, the compiler creates a plurality of virtual registers in the memory for storage of variables defined in the source program. Means are provided to ensure that the same virtual register is never assigned to more than once on any dynamic execution path.