Abstract: A firmware protection module implements a hybrid firmware protection scheme on a computing device. The firmware protection module intercepts a message from a processor to a memory of the computing device. The message includes a command and an address in the memory corresponding to a firmware module stored in the module. The firmware protection module determines whether the command in the message is prohibited and whether the address in the message is protected. Responsive to a determination that the command is prohibited and the address is protected, the firmware protection module prevents at least a portion of the message from reaching the memory.

Abstract: A method for producing a thermal infrared sensor array in a vacuum-filled wafer-level housing with particularly small dimensions, consisting of at least two wafers, a cover wafer and a central wafer comprising multiple infrared-sensitive sensor pixels on a respective thin slotted membrane over a heat-insulating cavity is disclosed. A method for producing a high-resolution monolithic silicon micromechanical thermopile array sensor using wafer level packaging technology, wherein the sensor achieves a particularly high spatial resolution capability and a very high filling degree with very small housing dimensions, in particular a very low overall thickness, and can be inexpensively produced using standard CMOS processes. This is achieved in that the cover wafer is first rigidly mechanically connected to the provided central wafer comprising the sensor pixels with the infrared-sensitive pixels by means of wafer bonding, and the central wafer is then thinned out from the wafer rear face to a specified thickness.

Abstract: High-resolution thermopile infrared sensor array having a plurality of parallel signal processing channels for the signals of a sensor array and a digital port for serially emitting the signals. Each signal processing channel comprises at least one analog to digital converter and is assigned a memory for storing the results of the analog to digital converters. Power consumption of the infrared sensor array is reduced in the case of a sensor array with at least 16 rows and at least 16 columns, in that no more than 8 or 16 pixels are connected to a signal processing channel. The number of signal processing channels corresponds to at least 4 times the number of rows. Some of the signal processing channels are disposed in the intermediate space between the pixels and others are disposed in an outer edge region of the sensor chip surrounding the sensor array along with other electronics.

Abstract: A high-resolution thermopile infrared sensor array having monolithically integrated signal processing and a plurality of parallel signal processing channels for the signals from pixels of a sensor array, and a digital port for the serial output of the pixel signals are provided, wherein the sensor array is located on one or more sensor chips. The thermal piled infrared sensor array possesses low power loss, high integration density and high thermal and geometric resolution. Each signal processing channel (K1 . . . KN) has at least one analogue/digital converter (ADC), and is assigned a memory region in a memory (RAM) for storing the signals from the pixels (SE).

Abstract: High-resolution thermopile infrared sensor array having a plurality of parallel signal processing channels for the signals of a sensor array and a digital port for serially emitting the signals. Each signal processing channel comprises at least one analog to digital converter and is assigned a memory for storing the results of the analog to digital converters. Power consumption of the infrared sensor array is reduced in the case of a sensor array with at least 16 rows and at least 16 columns, in that no more than 8 or 16 pixels are connected to a signal processing channel. The number of signal processing channels corresponds to at least 4 times the number of rows. Some of the signal processing channels are disposed in the intermediate space between the pixels and others are disposed in an outer edge region of the sensor chip surrounding the sensor array along with other electronics.

Abstract: A thermal infrared sensor array in a wafer-level package includes at least one infrared-sensitive pixel produced using silicon micro mechanics, comprising a heat-isolating cavity in a silicon substrate surrounded by a silicon edge, and a thin membrane connected to the silicone edge by of thin beams. The cavity extends through the silicon substrate to the membrane, and there are slots between the membrane, the beams and the silicon edge. A plurality of infrared-sensitive individual pixels are arranged in lines or arrays and are designed in a CMOS stack in a dielectric layer, forming the membrane, and are arranged between at least one cover wafer which is designed in the form of a cap and has a cavity and a base wafer. The cover wafer, the silicon substrate and the base wafer are connected to one another in a vacuum-tight manner and enclosing a gas vacuum.

Abstract: A firmware protection module implements a hybrid firmware protection scheme on a computing device. The firmware protection module intercepts a message from a processor to a memory of the computing device. The message includes a command and an address in the memory corresponding to a firmware module stored in the module. The firmware protection module determines whether the command in the message is prohibited and whether the address in the message is protected. Responsive to a determination that the command is prohibited and the address is protected, the firmware protection module prevents at least a portion of the message from reaching the memory.

Abstract: High-resolution thermopile infrared sensor array having a plurality of parallel signal processing channels for the signals of a sensor array and a digital port for serially emitting the signals. Each signal processing channel comprises at least one analog to digital converter and is assigned a memory for storing the results of the analog to digital converters. Power consumption of the infrared sensor array is reduced in the case of a sensor array with at least 16 rows and at least 16 columns, in that no more than 8 or 16 pixels are connected to a signal processing channel. The number of signal processing channels corresponds to at least 4 times the number of rows. Some of the signal processing channels are disposed in the intermediate space between the pixels and others are disposed in an outer edge region of the sensor chip surrounding the sensor array along with other electronics.

Abstract: A high-resolution thermopile infrared sensor array having monolithically integrated signal processing and a plurality of parallel signal processing channels for the signals from pixels of a sensor array, and a digital port for the serial output of the pixel signals are provided, wherein the sensor array is located on one or more sensor chips. The thermal piled infrared sensor array possesses low power loss, high integration density and high thermal and geometric resolution. Each signal processing channel (K1 . . . KN) has at least one analogue/digital converter (ADC), and is assigned a memory region in a memory (RAM) for storing the signals from the pixels (SE).

Abstract: A high-resolution thermopile infrared sensor array having monolithically integrated signal processing and a plurality of parallel signal processing channels for the signals from pixels of a sensor array, and a digital port for the serial output of the pixel signals are provided, wherein the sensor array is located on one or more sensor chips. The thermal piled infrared sensor array possesses low power loss, high integration density and high thermal and geometric resolution. Each signal processing channel (K1 . . . KN) has at least one analogue/digital converter (ADC), and is assigned a memory region in a memory (RAM) for storing the signals from the pixels (SE).

Abstract: High-resolution thermopile infrared sensor array having a plurality of parallel signal processing channels for the signals of a sensor array and a digital port for serially emitting the signals. Each signal processing channel comprises at least one analog to digital converter and is assigned a memory for storing the results of the analog to digital converters. Power consumption of the infrared sensor array is reduced in the case of a sensor array with at least 16 rows and at least 16 columns, in that no more than 8 or 16 pixels are connected to a signal processing channel. The number of signal processing channels corresponds to at least 4 times the number of rows. Some of the signal processing channels are disposed in the intermediate space between the pixels and others are disposed in an outer edge region of the sensor chip surrounding the sensor array along with other electronics.

Abstract: A thermal infrared sensor array in a wafer-level package includes at least one infrared-sensitive pixel produced using silicon micro mechanics, comprising a heat-isolating cavity in a silicon substrate surrounded by a silicon edge, and a thin membrane connected to the silicone edge by of thin beams. The cavity extends through the silicon substrate to the membrane, and there are slots between the membrane, the beams and the silicon edge. A plurality of infrared-sensitive individual pixels are arranged in lines or arrays and are designed in a CMOS stack in a dielectric layer, forming the membrane, and are arranged between at least one cover wafer which is designed in the form of a cap and has a cavity and a base wafer. The cover wafer, the silicon substrate and the base wafer are connected to one another in a vacuum-tight manner and enclosing a gas vacuum.

Abstract: A high-resolution thermopile infrared sensor array having monolithically integrated signal processing and a plurality of parallel signal processing channels for the signals from pixels of a sensor array, and a digital port for the serial output of the pixel signals are provided, wherein the sensor array is located on one or more sensor chips. The thermal piled infrared sensor array possesses low power loss, high integration density and high thermal and geometric resolution. Each signal processing channel (K1 . . . KN) has at least one analogue/digital converter (ADC), and is assigned a memory region in a memory (RAM) for storing the signals from the pixels (SE).