Abstract: A bulbous valvuloplasty balloon is described that maintains its bulbous shape in its final deployed configuration along with the method of use for post dilation of a TAVR device. The bulbous balloon has two larger diameter bulb segments located on each side of a smaller diameter waist and can be used to post dilate a TAVR device that has been implanted at the site of a stenotic aortic valve. The post dilation causes deformation of the underlying tissues residing outside of the TARV stent structure.

Abstract: A bulbous valvuloplasty balloon is described that maintains its bulbous shape in its final deployed configuration along with the method of use for post dilation of a TAVR device. The bulbous balloon has two larger diameter bulb segments located on each side of a smaller diameter waist and can be used to post dilate a TAVR device that has been implanted at the site of a stenotic aortic valve. The post dilation causes deformation of the underlying tissues residing outside of the TARV stent structure.

Abstract: A nasal breathing strip comprising a resiliently-deformable planar plastic strip having an inner surface adjacent a user's nose skin. Adherent portions adhere to the wearer's skin on opposite sides of the nose bridge to maintain the strip in a biased folded condition. In a first embodiment, a non-adherent central portion of the inner surface between the adherent portions is also coated with adhesive overlain by a non-adhesive material formed from paper, cloth, plastic, or combinations thereof. The non-adherent central portion pads the fulcrum function of the nose bridge and prevents irritation of skin on the bridge. Preferably the non-adhesive material is also non-allergenic for skin contact. In a second embodiment, the central portion remains free of adhesive during manufacture of the nasal strip and thus is inherently non-adherent and exposed solely to atmospheric air. Alternatively, the non-adherent central portion may be covered by a lubricating agent.

Abstract: A method and system for the enhanced efficiency of data transfers from memory to multiple processors in a data processing system. Each of the multiple processors has an associated buffer for storing data transferred via a common bus which couples the processors and memory together. Each of the multiple processors continually monitors the common bus and is capable of asserting a selected control signal in response to an attempted activity of another one of the multiple processors which would violate data coherency within the data processing system during a particular period of time following the attempted activity. Data is transferred from memory to a buffer associated with one of the multiple processors and stored in the buffer in response to a request from the processor associated with the buffer prior to expiration of the particular period of time and prior to a determination of whether or not this transfer will result in a possible data coherency problem.

Abstract: A system and method are provided that use a determination of bad data parity and the state of an error signal (Derr.sub.--) as a functional signal indicating a specific type of error in a particular system component. If the Derr.sub.-- signal is active, the parity error recognized by the CPU was caused by a correctable condition in a data providing device. In this instance, the processor will read the corrected data from a buffer without reissuing a fetch request. When the CPU finds a parity error, but Derr.sub.-- is not active a more serious fault condition is identified (bus error or uncorrectable multibit error) requiring a machine level interrupt, or the like. And, when no parity is found by the CPU and Derr.sub.-- is not active, then the data is known to be valid and the parity/ECC latency is eliminated, thereby saving processing cycle time.

Abstract: A method and system are provided for communicating between devices. A signal is output from a first device. In response to the signal, at least one action is initiated by a second device. An indication is output of whether the second device completed the action and of whether operation of the second device is independent of the first device reoutputting the signal.

Abstract: A method and system in a data processing system for transferring data from a first device to a second device within the data processing system. The data processing system includes a data bus, an address bus, a first address space associated with a memory and a second address space associated with an input/output device. Initially, an operation request package is transmitted to a second device from a first device, which informs the second device of the total amount of data to be transferred. A transfer signal is then transmitted in the data processing system. The transfer signal identifies the transfer as a transfer concerning an address in the second address space associated with the input/output device. A first address package is then transmitted to the second device from the first device on the address bus. The first address package includes a transfer identifier, a first identifier associated with the first device and a second identifier associated with the second device.

Abstract: An efficient multiprocessor address transfer mechanism is utilized within a data processing system including a plurality of bus devices. The present invention places control of the flow of address bus operations within the system controller rather than the bus devices, e.g., a master processor. The system controller issues an address bus grant, in response to an address bus request from a particular bus device, and shortly after that issues another signal notifying the granted bus device that it must now disable the address bus. Furthermore, upon receipt of the signal indicating disablement of the address bus, other bus devices may then snoop, or sample, the address bus.

Abstract: A system and method which utilizes a unique bus protocol in conjunctions plural Dval.sub.-- control signals to minimize the dead time between blocks of data being transferred between components is a data processing system. The present invention introduces another latch-to-latch data valid control signal and alternates the usage of this signal during back to back data transfers from the same or different bus devices. In this manner the restore and tristate dead cycles are totally overlapped with the data transfer and the minimum possible number of dead cycle(s) is achieved between different blocks of data transfers. With the method of the present invention, data providers alternately activate the Dval.sub.-- signals and data receivers look at all Dval.sub.-- signals and if any one of them is active, then the data is considered valid and can be read.

Abstract: A multiprocessor system utilizing a plurality of bus devices coupled via a shared bus utilizes a specially coded signal to notify a bus device initiating a read or a read with intent to modify operation that the requested data, or cache line, is in a modified state within a cache of another bus device. Unlike the modified response signal, this special signal is sent along with the requested data from the one bus device to the requesting bus device, indicating that this data has priority over any data being sent from the memory system coupled to the shared bus. The present invention allows for cache-to-cache and cache-to-memory-and-cache operations.