Patents by Inventor Michael Sedmak

Michael Sedmak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8667324
    Abstract: In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is compared with the quality rank of the non-allocated cache elements. If a non-allocated cache element has a lower quality rank than the allocated cache element, the non-allocated cache element is swapped in for the allocated cache element.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: March 4, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Patent number: 8661289
    Abstract: In one embodiment, a CPU cache management system is provided. The CPU management system includes, for example, a CPU chip and cache management logic. The CPU chip include cache elements that are initially in use and spare cache elements that not initially in use. The cache management logic determines whether currently-used cache elements are faulty. If a cache element is determined to be faulty, the cache management logic schedules a reboot of the computer and swaps in a spare cache element for the faulty currently-used cache element during the reboot.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: February 25, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20120173854
    Abstract: Methods and apparatuses are provided for an efficient technique for processing registers having a known value while improving processor performance. The apparatus comprises a processor having a plurality of physical registers available for use in computations and a decoder for determining that a logical register contains a known value. A renaming unit maps the logical register containing the known value to an address outside an address range for the plurality of physical registers once the known value is determined. Thereafter, scheduling and execution units perform computations using the known value without storing the known value in one of the plurality of physical registers. The method comprises determining that a logical register of a processor has a known value and then mapping that logical register to a physical register address outside an expected range of physical register addresses; which indicates that the logical register represents the known value.
    Type: Application
    Filed: December 29, 2010
    Publication date: July 5, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Jay FLEISCHMAN, Debjit Das Sarma, Michael SEDMAK
  • Publication number: 20120005459
    Abstract: Methods and apparatuses are provided for increasing processor performance and energy saving via eliminating physical data movement to accomplish a move instruction. The apparatus comprises a first plurality of available physical registers mapped to a second plurality of logical registers, including a source logical register and a destination logical register. A renaming unit remaps the destination logical register to the same physical register mapping as the source logical register in response to a move instruction. In this way, the move instruction is effectively executed without moving data between physical registers. A method is provided for increasing processor performance and energy saving via eliminating physical data movement to accomplish a move instruction.
    Type: Application
    Filed: December 28, 2010
    Publication date: January 5, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Jay FLEISCHMAN, Matthew M. CRUM, Michael ESTLICK, Ranganathan SUDHAKAR, Emil TALPES, Ganesh VENKATARAMANAN, Barry J. Arnold, Michael Sedmak
  • Patent number: 7917804
    Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: March 29, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Patent number: 7694174
    Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: April 6, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Patent number: 7694175
    Abstract: Systems and methods for conducting processor health-checks are provided. In one embodiment, a method for evaluating the status of a processor is provided. The method includes, for example, initializing and executing an operating system, de-allocating the processor from the available pool or system resources and performing a health-check on the processor while the operating system is executing.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: April 6, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Ray Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Patent number: 7673171
    Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: March 2, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Patent number: 7607038
    Abstract: In one embodiment, a method for repairing a faulty cache element is provided. Once a monitored cache element is determined to be faulty, the system stores the repair information, and cache configuration in an EEPROM or non-volatile memory on the CPU module. Then the computer is rebooted. During the reboot, the faulty cache element is repaired by being swapped out for a spare cache element based on the information stored in the EEPROM or the non-volatile memory.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: October 20, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Patent number: 7603582
    Abstract: In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is compared with the quality rank of the non-allocated cache elements. If a non-allocated cache element has a lower quality rank than the allocated cache element, the non-allocated cache element is swapped in for the allocated cache element.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: October 13, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Patent number: 7533293
    Abstract: In one embodiment, a CPU cache management system is provided. The CPU management system includes, for example, a CPU chip and cache management logic. The CPU chip include cache elements that are initially in use and spare cache elements that not initially in use. The cache management logic determines whether currently-used cache elements are faulty. If a cache element is determined to be faulty, the cache management logic schedules a reboot of the computer and swaps in a spare cache element for the faulty currently-used cache element during the reboot.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: May 12, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Patent number: 7523346
    Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: April 21, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20080005616
    Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.
    Type: Application
    Filed: February 17, 2006
    Publication date: January 3, 2008
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20060248313
    Abstract: In one embodiment, a CPU cache management system is provided. The CPU management system includes, for example, a CPU chip and cache management logic. The CPU chip include cache elements that are initially in use and spare cache elements that not initially in use. The cache management logic determines whether currently-used cache elements are faulty. If a cache element is determined to be faulty, the cache management logic schedules a reboot of the computer and swaps in a spare cache element for the faulty currently-used cache element during the reboot.
    Type: Application
    Filed: February 17, 2006
    Publication date: November 2, 2006
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20060248314
    Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.
    Type: Application
    Filed: February 17, 2006
    Publication date: November 2, 2006
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20060248312
    Abstract: In one embodiment, a CPU cache management system is provided. The CPU management system includes, for example, a CPU chip and cache management logic. The CPU chip include cache elements that are initially in use and spare cache elements that not initially in use. The cache management logic determines whether currently-used cache elements are faulty. If a cache element is determined to be faulty, the cache management logic schedules a reboot of the computer and swaps in a spare cache element for the faulty currently-used cache element during the reboot.
    Type: Application
    Filed: February 17, 2006
    Publication date: November 2, 2006
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20060248392
    Abstract: In one embodiment, a method for repairing a faulty cache element is provided. Once a monitored cache element is determined to be faulty, the system stores the repair information, and cache configuration in an EEPROM or non-volatile memory on the CPU module. Then the computer is rebooted. During the reboot, the faulty cache element is repaired by being swapped out for a spare cache element based on the information stored in the EEPROM or the non-volatile memory.
    Type: Application
    Filed: February 17, 2006
    Publication date: November 2, 2006
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20060236035
    Abstract: In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is compared with the quality rank of the non-allocated cache elements. If a non-allocated cache element has a lower quality rank than the allocated cache element, the non-allocated cache element is swapped in for the allocated cache element.
    Type: Application
    Filed: February 17, 2006
    Publication date: October 19, 2006
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20060230308
    Abstract: Systems and methods for conducting processor health-checks are provided. In one embodiment, a method for evaluating the status of a processor is provided. The method includes, for example, initializing and executing an operating system, de-allocating the processor from the available pool or system resources and performing a health-check on the processor while the operating system is executing.
    Type: Application
    Filed: February 17, 2006
    Publication date: October 12, 2006
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20060230254
    Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.
    Type: Application
    Filed: February 17, 2006
    Publication date: October 12, 2006
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak