Abstract: A method for using a graphics processor by an electronic device for subdividing an input image into multiple sub-regions. For each particular sub-region, a data structure is created that identifies one or more primitives that are visible in each quad of the particular sub-region. Existing coverage of one or more quads is erased based on graphics state (GState) information resulting in surviving coverage for one or more quads.

Abstract: A method for executing instructions in a thread processing environment includes determining a multiple requirements that must be satisfied and resources that must be available for executing multiple instructions. The multiple instructions are encapsulated into a schedulable structure. A header is configured for the schedulable structure with information including the determined multiple requirements and resources. The schedulable structure is schedule for executing each of the multiple instructions using the information.

Abstract: A method for using a graphics processor by an electronic device for subdividing an input image into multiple sub-regions. For each particular sub-region, a data structure is created that identifies one or more primitives that are visible in each quad of the particular sub-region. Existing coverage of one or more quads is erased based on graphics state (GState) information resulting in surviving coverage for one or more quads.

Abstract: A method for executing instructions in a thread processing environment includes determining a multiple requirements that must be satisfied and resources that must be available for executing multiple instructions. The multiple instructions are encapsulated into a schedulable structure. A header is configured for the schedulable structure with information including the determined multiple requirements and resources. The schedulable structure is schedule for executing each of the multiple instructions using the information.

Abstract: A method, in accordance with an embodiment of the invention, includes detecting a memory page miss associated with a thread operating on a Graphics Processing Unit (GPU). A request can be issued to receive the memory page associated with the memory page miss. There can be a switch into a runahead mode. During the runahead mode, a future memory page miss can be detected. During the runahead mode, a request can be issued to receive the future memory page associated with the future memory page miss.

Abstract: Disclosed is a computer in which an error caused by an intermittent failure is corrected by using a misprediction recovery mechanism which performs recovery processing if, after having predicted a branch destination of a branch instruction and speculatively executed an instruction at the predicted branch destination, it turns out that the branch prediction was wrong. The computer includes an error detection mechanism for detecting an error in logic operation of the computer, and an instruction re-execution mechanism for correcting an error caused by an intermittent failure when an error is detected by the error detection mechanism, by restoring the computer, using the misprediction recovery mechanism, to a state that existed before the occurrence of the error, and by re-executing a sequence of instructions including the instruction where the error is detected.