Patents by Inventor Michael Sheets
Michael Sheets has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11915329Abstract: An online agricultural system manages and optimizes interactions of entities within the system to enable the execution of transaction and the transportation of crop products. The online agricultural system accesses historic and environmental data describing factors that may impact crop product transactions and/or transportation to determine market prices for crop products and crop product transportation. Responsive to receiving a request from an entity, the online agricultural system determines an optimal transaction for the entity, such as a price for selling a crop product, an available crop product for purchase, or a transportation opportunity to transport a crop product.Type: GrantFiled: September 7, 2021Date of Patent: February 27, 2024Assignee: INDIGO AG, INC.Inventors: David Patrick Perry, Barry Loyd Knight, Eric Michael Jeck, Rachel Ariel Raymond, Neal Hitesh Rajdev, Geoffrey Albert von Maltzahn, Robert Berendes, Nathan Post, Philip Gabriel Sheets-Poling, Rodney Connor, Jonathan Hennek, Ean Shaughnessy Wahl Mullins
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Publication number: 20190279321Abstract: Methods, apparatuses, and processor-executable instructions for proving public disclosure of an idea using blockchain technology are provided. For instance, in an aspect of the present disclosure, an example method performed by a controller for proving existence and public disclosure of an idea. In some examples, such an example method includes a controller entity receiving an idea from a source entity, proving existence of the idea by placing a representation of the idea on a first set of blockchains, and proving public availability of the idea at one or more instances by placing a representation of a state of a database of publicly served ideas on a second set of blockchains.Type: ApplicationFiled: March 12, 2019Publication date: September 12, 2019Inventors: Eli Michael Sheets, Kitrick Brian Sheets
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Patent number: 9949495Abstract: A sliced jumbo tender of a meat tender or poultry breast resulting in strips having a desired weight and thickness with minimal losses. The sliced tender includes two diagonal cuts across and through the tender to yield three strips which are substantially the same in weight and thickness.Type: GrantFiled: January 30, 2017Date of Patent: April 24, 2018Assignee: MAS MARKETING HOLDING COMPANY, LLCInventors: Mike Ensley, Andres Garcia, Gordon Tatro, Michael Sheets, Mark Sosebee
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Publication number: 20170231238Abstract: A sliced jumbo tender of a meat tender or poultry breast resulting in strips having a desired weight and thickness with minimal losses. The sliced tender includes two diagonal cuts across and through the tender to yield three strips which are substantially the same in weight and thickness.Type: ApplicationFiled: January 30, 2017Publication date: August 17, 2017Inventors: Mike Ensley, Andres Garcia, Gordon Tatro, Michael Sheets, Mark Sosebee
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Patent number: 9629373Abstract: A method of processing a jumbo tender of a meat tender or poultry breast into strips having a desired weight and thickness with minimal losses requires two diagonal cuts across and through the jumbo to yield three portions which are substantially the same in weight and thickness.Type: GrantFiled: March 1, 2013Date of Patent: April 25, 2017Assignee: MAS Marketing Holding Company, LLCInventors: Mike Ensley, Andres Garcia, Gordon Tatro, Michael Sheets, Mark Sosebee
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Publication number: 20160183540Abstract: A method of processing a jumbo tender of a meat tender or poultry breast into strips having a desired weight and thickness with minimal losses requires two diagonal cuts across and through the jumbo to yield three portions which are substantially the same in weight and thickness.Type: ApplicationFiled: December 3, 2015Publication date: June 30, 2016Inventors: Mike Ensley, Andres Garcia, Gordon Tatro, Michael Sheets, Mark Sosebee
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Patent number: 9298531Abstract: A method and apparatus to operate a watchdog timer having a first time out period in a processing system. The watchdog timer receives an indication of a change in a mode of operation in the processing system. In response to the change in the mode of operation of the processing system, the watchdog timer changes the time out period to a second time out period corresponding to the new mode of operation.Type: GrantFiled: March 2, 2015Date of Patent: March 29, 2016Assignee: Cypress Semiconductor CorporationInventors: Michael Sheets, David G. Wright
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Patent number: 8977911Abstract: A method and apparatus to operate a watchdog timer having a first time out period in a processing system. The watchdog timer receives an indication of a change in a mode of operation in the processing system. In response to the change in the mode of operation of the processing system, the watchdog timer changes the time out period to a second time out period corresponding to the new mode of operation.Type: GrantFiled: February 12, 2013Date of Patent: March 10, 2015Assignee: Cypress Semiconductor CorporationInventors: Michael Sheets, David G. Wright
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Patent number: 8832475Abstract: A system includes a context file to store multiple contexts corresponding to different power modes of an electronic system, and a domain control device to generate control signals based, at least in part, on a context from the context file. The electronic system is configured to transition to a power mode corresponding to the context responsive to the control signals.Type: GrantFiled: May 10, 2010Date of Patent: September 9, 2014Assignee: Cypress Semiconductor CorporationInventor: Michael Sheets
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Patent number: 8705309Abstract: Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC's state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element.Type: GrantFiled: June 11, 2013Date of Patent: April 22, 2014Assignee: Cypress Semiconductor CorporationInventors: Michael Sheets, Timothy John Williams
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Publication number: 20130336081Abstract: Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC's state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element.Type: ApplicationFiled: June 11, 2013Publication date: December 19, 2013Inventors: Michael Sheets, Timothy J. Williams
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Patent number: 8462576Abstract: Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be disturbed in different locations on the IC for better coverage.Type: GrantFiled: November 22, 2011Date of Patent: June 11, 2013Assignee: Cypress Semiconductor CorporationInventors: Michael Sheets, Timothy Williams
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Patent number: 8375258Abstract: A method and apparatus to operate a watchdog timer having a first time out period in a processing system. The watchdog timer receives an indication of a change in a mode of operation in the processing system. In response to the change in the mode of operation of the processing system, the watchdog timer changes the time out period to a second time out period corresponding to the new mode of operation.Type: GrantFiled: April 1, 2010Date of Patent: February 12, 2013Assignee: Cypress Semiconductor CorporationInventors: Michael Sheets, David G. Wright
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Publication number: 20120176854Abstract: Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be disturbed in different locations on the IC for better coverage.Type: ApplicationFiled: November 22, 2011Publication date: July 12, 2012Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Michael Sheets, Timothy Williams
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Patent number: 8111577Abstract: Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC's state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element.Type: GrantFiled: September 19, 2007Date of Patent: February 7, 2012Assignee: Cypress Semiconductor CorporationInventors: Michael Sheets, Timothy Williams
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Patent number: 8064281Abstract: Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC's state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element.Type: GrantFiled: September 19, 2007Date of Patent: November 22, 2011Assignee: Cypress Semiconductor CorporationInventors: Michael Sheets, Timothy Williams
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Publication number: 20080259702Abstract: Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC's state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element.Type: ApplicationFiled: September 19, 2007Publication date: October 23, 2008Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Michael Sheets, Timothy Williams