Abstract: A processing device determines a measured slope value of a portion of a programming voltage distribution of memory cells of a memory sub-system. The measured slope value of the portion of the programming voltage distribution is compared to a threshold slope value to generate a comparison result. An adjusted program voltage level is determined in view of the comparison result. A programming process is executed using the adjusted program voltage level as a starting voltage level.

Abstract: Aspects of the present disclosure are directed to performing varying frequency memory sub-system background scans using either or both a timer and an I/O event limit. This can be accomplished by identifying a background scan trigger event from one of multiple possible types of background scan trigger events, such as a timer expiration or reaching an event count limit. In response to the background scan trigger event, a background scan can be initiated on a memory portion. The background scan can produce results, such as CDF-based data. When a metric based on the results exceeds a background scan limit, a refresh relocation can be performed and logged. A metric can be generated based on the CDF-based data, obtained error recovery depth data, or refresh relocation event data. When the metric is above or below corresponding background scan thresholds, a background scan frequency can be adjusted.

Abstract: The present disclosure is directed to read sample offset most probable bit operation associated with a memory component. A processing device generates a first set of read data associated with a memory component, the first set of read data comprising a first sequence of bit values. The processing device generates a second set of read data associated with the memory component, the second set of read data comprising a second sequence of bit values. The processing device generates a third set of read data associated with the memory component, the third set of read data comprising a third sequence of bit values. A most probable bit operation is performed to compare the first sequence of bit values, the second sequence of bit values, and the third sequence of bit values to generate and store a most probable bit sequence.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including determining first values of a metric that is indicative of a margin for a valley that is located between programming distributions of a memory cell of the memory device. The operations further include determining second values of the metric based on the first values, and adjusting valley margins of the memory cell in accordance with the second values of the metric.

Abstract: A system can include a memory device and a processing device to perform operations that include performing a block family calibration scan of the memory device, wherein the calibration scan comprises a plurality of scan iterations, wherein each scan iteration is initiated in accordance with at least one threshold scan criterion, and wherein each scan iteration comprises identifying at least one first voltage bin, wherein each first voltage bin is associated with a plurality of read level offsets, identifying, according to a block family creation order, an oldest block family from a plurality of block families associated with the first voltage bin, and updating at least one bin pointer of the oldest block family based on a data state metric of at least one block of the oldest block family.

Abstract: A system includes a memory device and a processing device, operatively coupled to the memory device, the processing device to perform operations comprising: measuring one of a temperature voltage shift or a read bit error rate of fixed data stored in the memory device in response to detecting a power on of the memory device, the fixed data having been programmed in response to detecting a power loss; estimating an amount of time for which the memory device was powered off based on results of the measuring; and in response to the amount of time satisfying a threshold criterion, updating a value for a temporal voltage shift of a block family based on the amount of time.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric of a memory page; responsive to the data state metric satisfying a first threshold criterion, determining a value of a voltage distribution metric associated with the page; and responsive to the voltage distribution metric value satisfying a second threshold criterion, performing a media management operation with respect to a block associated with the page.

Abstract: A block family associated with a memory device is created. The block family is associated with a threshold voltage offset bin. A set of read level voltage offsets is determined such that, applying the set of read level voltage offsets to a base read level threshold voltage associated with the block family, result in a suboptimal error rate not exceeding a maximum allowable error rate. The determined set of read level offsets is associated with the threshold voltage offset bin by updating a block family metadata.

Abstract: A system includes a memory array with memory cells and a processing device coupled thereto. The processing device performs program targeting operations that include to: determine a set of difference error counts corresponding to programming distributions of the memory array; identify, based on a comparison of the set of difference error counts, valley margins corresponding to the programming distributions; select, based on values of the valley margins, a program targeting rule from a set of rules; perform, based on the program targeting rule, a program targeting operation to adjust a voltage level associated with an erase distribution of the memory array; determine a bit error rate (BER) of the memory array; in response to the BER satisfying a BER control value, reduce the voltage level by a voltage step; and in response to the BER not satisfying the BER control value, increase the voltage level by the voltage step.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a first temperature level of a first block family associated with a memory device; identify a second temperature level of a second block family associated with the memory device; determine if a condition is satisfied based on the first temperature level and the second temperature level; and in response to the condition being satisfied, combine the first block family and the second block family to generate a combined block family.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to determine that a first block family of a plurality of block families of the memory device and a second block family of the plurality of block families satisfy a proximity condition; determine whether the first block family and the second block family meet a time-based combining criterion corresponding to the proximity condition; and responsive to determining that the first block family and the second block family meet the time-based combining criterion, merge the first block family and the second block family.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan process on a plurality of block families of the memory device; responsive to determining, based on the scan process, that a first block family of the plurality of block families and a second block family of the plurality of block families meet a combining criterion, merge the first block family and the second block family; and responsive to determining that a terminating condition has been satisfied, terminate the scan process.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a first temperature level of a first block family associated with a memory device; identify a second temperature level of a second block family associated with the memory device; determine if a condition is satisfied based on the first temperature level and the second temperature level; and in response to the condition being satisfied, combine the first block family and the second block family to generate a combined block family.

Abstract: A system can include a memory device and a processing device to perform operations that include identifying voltage offset bins of the memory device, each of the first voltage offset bins satisfying a first age threshold criterion, identifying one or more second voltage offset bins of the memory device, each of the second voltage offset bins satisfying a second age threshold criterion, identifying a first block family associated with one of the first voltage offset bins, and performing a first scan of a first block of the first block family by: identifying, based on determined values of the first data state metric, a first identified voltage offset bin, and identifying one or more values of a second data state metric in scan metadata generated by a second scan, and identifying, based on the one or more values of the second data state metric, a second identified voltage offset bin.

Abstract: One or more data units at a memory device and that are associated with one or more dice of a die group comprising a plurality of dice are programmed. A voltage offset bin associated with the plurality of dice in the die group is determined based on a subset of dice of the die group.

Abstract: A set of two or more block families associated with a bin boundary of a first voltage bin is identified. A determination of at least a first voltage for a first block family of the plurality of block families and a second voltage for a second block family of the plurality of block families based on values of a data state metric for each of the plurality of block families. In response to a determination that a difference between the first voltage and the second voltage satisfies a block family combination criterion, the second block family is merged with the first block family.

Abstract: A system can include a memory device and a processing device to perform operations that include identifying voltage offset bins of the memory device, each of the first voltage offset bins satisfying a first age threshold criterion, identifying one or more second voltage offset bins of the memory device, each of the second voltage offset bins satisfying a second age threshold criterion, identifying a first block family associated with one of the first voltage offset bins, and performing a first scan of a first block of the first block family by: identifying, based on determined values of the first data state metric, a first identified voltage offset bin, and identifying one or more values of a second data state metric in scan metadata generated by a second scan, and identifying, based on the one or more values of the second data state metric, a second identified voltage offset bin.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to create a first block family comprising a first set of blocks that have been programmed within at least one of a first specified time window or a first specified temperature window, wherein each block associated with the first block family is associated with a first set of read level offsets; create, a second block family comprising a second set of blocks that have been programmed within at least one of a second specified time window following the first specified time window or a second specified temperature window, wherein each block associated with the second block family is associated with a second set of read level offsets; and responsive to a determining that a threshold criterion is satisfied, combine the first and second block family.

Abstract: A processing device establishes a first data group of memory cells of a memory sub-system and a second data group of memory cells of the memory sub-system. A first portion of the first data group is programmed at a threshold voltage level to set a first embedded data value. A second portion of the second data group of memory cells is programmed at the threshold voltage level offset by an offset voltage level to set a second embedded data value.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to open a first block family associated with the memory device; assign a first cursor of a plurality of cursors of the memory device to the first block family; responsive to programming a first block associated with the first cursor, associate the first block with the first block family; open, while the first block family is open, a second block family associated with the memory device; assign a second cursor of the plurality of cursors of the memory device to the second block family; and responsive to programming a second block associated with the second cursor, associate the second block with the second block family.