Abstract: A solution for fabricating a structure including a light guiding structure is provided. The light guiding structure can be formed of a fluoropolymer-based material and include one or more regions, each of which is filled with a fluid transparent to radiation having a target wavelength, such as ultraviolet radiation. The region(s) can be created using a filler material, which is at least substantially enclosed by the fluoropolymer-based material and subsequently removed from each region. The structure can further include at least one optical element integrated into the light guiding structure.

Abstract: A semiconductor structure including an anodic aluminum oxide layer is described. The anodic aluminum oxide layer can include a plurality of pores extending to an adjacent surface of the semiconductor structure. A filler material can penetrate at least some of the plurality of pores and directly contact the surface of the semiconductor structure. In an illustrative embodiment, multiple types of filler material at least partially fill the pores of the aluminum oxide layer.

Abstract: A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.

Abstract: An ultraviolet (UV) footwear illuminator for footwear treatment is disclosed. In one embodiment, the UV footwear illuminator includes an insert adapted for placement in an article of footwear. At least one UV radiation source is located in the insert and is configured to emit UV radiation in the footwear through a transparent window region formed in the insert. A control unit is configured to control at least one predetermined UV radiation characteristics associated with the radiation emitted from each UV radiation source. A power supply is configured to power each UV radiation source and the control unit.

Abstract: A structured substrate configured for epitaxial growth of a semiconductor layer thereon is provided. Structures can be formed on a side of the structured substrate opposite that of the growth surface for the semiconductor layer. The structures can include cavities and/or pillars, which can be patterned, randomly distributed, and/or the like. The structures can be configured to modify one or more properties of the substrate material such that growth of a higher quality semiconductor layer can be obtained.

Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.

Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.

Abstract: Flash light-generating methods and systems are provided, which, in one aspect, include: obtaining one or more measurements of existing light on or around an illumination target; ascertaining a desired color attribute(s) for a combined light to be provided on the illumination target, the combined light including the existing light and a flash light to be generated; determining a flash light spectral power distribution of illumination which achieves a combined light spectral power distribution of illumination on the illumination target having the desired color attribute(s), the determining using, in part, the measurement(s) of existing light, and the desired color attribute(s) for the combined light; and generating the flash light with the determined flash light spectral power distribution of illumination to provide the combined light on the illumination target having the combined light spectral power distribution of illumination with the desired color attribute(s).

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

Abstract: A system capable of detecting and/or sterilizing surface(s) of an object using ultraviolet radiation is provided. The system can include a disinfection chamber and/or handheld ultraviolet unit, which includes ultraviolet sources for inducing fluorescence in a contaminant and/or sterilizing a surface of an object. The object can comprise a protective suit, which is worn by a user and also can include ultraviolet sources for disinfecting air prior to the air entering the protective suit. The system can be implemented as a multi-tiered system for protecting the user and others from exposure to the contaminant and sterilizing the protective suit after exposure to an environment including the contaminant.

Abstract: A device including one or more low-conducting layers is provided. A low-conducting layer can be located below the channel and one or more attributes of the low-conducting layer can be configured based on a minimum target operating frequency of the device and a charge-discharge time of a trapped charge targeted for removal by the low-conducting layer or a maximum interfering frequency targeted for suppression using the low-conducting layer. For example, a product of the lateral resistance and a capacitance between the low-conducting layer and the channel can be configured to be larger than an inverse of the minimum target operating frequency and the product can be smaller than at least one of: the charge-discharge time or an inverse of the maximum interfering frequency.

Abstract: A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions.

Abstract: Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.

Abstract: A lateral semiconductor device and/or design including a space-charge generating layer and an electrode or a set of electrodes located on an opposite side of a device channel as contacts to the device channel is provided. The space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the contacts to the device channel.

Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.

Abstract: The current invention introduces a modulated field element incorporated into the semiconductor device outside the controlling electrode and active areas. This element changes its conductivity and/or dielectric properties depending on the electrical potentials of the interface or interfaces between the modulated field element and the semiconductor device and/or incident electromagnetic radiation. The element is either connected to only one terminal of the semiconductor device, or not connected to any terminal of a semiconductor device nor to its active area(s). Such an element can be used as modulated field plate, or a part of a field plate, as a passivation layer or its part, as a guard ring or its part, as a smart field or charge control element or its part, as a feedback element or its part, as a sensor element or its part, as an additional electrode or its part, as an electromagnetic signal path or its part, and/or for any other functions optimizing or modernizing device performance.

Abstract: A composite substrate configured for epitaxial growth of a semiconductor layer thereon is provided. The composite substrate includes multiple substrate layers formed of different materials having different thermal expansion coefficients. The thermal expansion coefficient of the material of the semiconductor layer can be between the thermal coefficients of the substrate layer materials. The composite substrate can have a composite thermal expansion coefficient configured to reduce an amount of tensile stress within the semiconductor layer at room temperature and/or an operating temperature for a device fabricated using the heterostructure.

Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.

Abstract: A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal.