Abstract: A method of calculating a position fix from satellite signal samples. The method comprises: obtaining first reference information produced during the calculation (120a) of a first position fix, the first position fix being the calculated position of a satellite-positioning receiver (5) at a first time; obtaining second reference information produced during the calculation (120b) of a second position fix, the second position fix being the calculated position of the receiver (5) at a second time; receiving a set of satellite signal samples generated by the receiver at a third time, or ranging measurements derived from such a set of satellite signal samples; and processing (140) the set of samples or the ranging measurements to calculate a third position fix. The processing (140) is assisted by the reference information produced during the calculation of the first and second position fixes.

Abstract: A magnetic target is provided for use with a magnetic proximity switch. The magnetic target includes a cylindrical body tube having an open end that partially defines a bore. A stationary magnet is located within the bore opposite the open end, and a movable magnet is disposed within the bore between the stationary magnet and the open end. An adjusting member is received into the bore, and a contact surface of the adjusting member engages the movable magnet. When the adjusting member is axially displaced, the contact surface causes a corresponding displacement of the movable magnet relative to the stationary magnet, eventually causing the magnetic flux field of each magnet to expand in a radial direction away from the longitudinal axis of each magnet. The stationary magnet and the movable magnet may be either axially-magnetized samarium-cobalt magnets or axially-magnetized neodymium magnets.

Abstract: An adapter conductively interconnects a chuck of a probe station and an instrument. The adapter includes a signal conductor conductively connected to the chuck and selectively connectable to a respective one of a ground potential, a bayonet connector output and a signal connection for the instrument. A guard potential conductor conductively connected to the chuck and selectively connectable to a one of a ground potential and a guard connection for the instrument; and a shield conductor connected to a ground potential.

Abstract: A controller has an interface, a buffer memory, a first set of registers for accessing the buffer memory, a second set of registers independent from the first set of registers for accessing the buffer memory, and a control unit for decoding and executing buffer memory access commands received by the interface to access the buffer memory through either the first or second set of registers.

Abstract: An adapter conductively interconnects a chuck of a probe station and an instrument. The adapter includes a signal conductor conductively connected to the chuck and selectively connectable to a respective one of a ground potential, a bayonet connector output and a signal connection for the instrument. A guard potential conductor conductively connected to the chuck and selectively connectable to a one of a ground potential and a guard connection for the instrument; and a shield conductor connected to a ground potential.

Abstract: An Ethernet controller has a buffer memory for receiving data packets, a data flow control unit for controlling the data flow to Ethernet controller, a packet counter, packet counter control logic for incrementing and decrementing the packet counter, a first register for storing a watermark, and a comparator logic coupled to the packet counter and the register for sending control signals to the data flow control unit.

Abstract: An integrated circuit device controls power up of an external device used for sensing a process variable independently of whether the integrated circuit device is in a low power sleep mode. Once the external device becomes operational the integrated device, even when still in the low power sleep mode, samples the process variable status of the external device. Low power timing circuits operational during the low power sleep mode control the power up of the external device and sampling of the process variable status thereof. After the sample of the process variable status is taken, the integrated circuit device may be brought out of the low power sleep mode to an operational mode when appropriate as determined from the sampled process variable status.

Abstract: A controller, in particular an Ethernet controller has a control unit operable to receive commands and data through an I/O interface; a plurality of registers arranged in a register block which is divided into a plurality of register banks, wherein at least one register controls a function of the controller; a register address unit having logic for accessing one of the plurality of registers by a plurality of addressing schemes, wherein the addressing schemes at least has a direct address provided by received data, a combined address provided by a partial address from a received command and a bank address stored in a bank register, and an address selected form a plurality of predetermined addresses through a received command.

Abstract: A semiconductor integrated circuit device uses two keeper cells per configuration and/or enable bit as dual redundant storage with error detection thereof. One of the two keeper cells stores a logic level and the other keeper cell stores the inverse of that logic level before the integrated circuit device goes into a low power mode. An exclusive OR (XOR) is performed on the outputs of the two keeper cells (a keeper cell pair) such that if the two keeper cells of the keeper cell pair do not have opposite logic levels stored therein, then the respective XOR outputs an error signal for that keeper cell pair and the error signal is used to force the integrated circuit device out of the low power mode, depending on software control, with or without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered.

Abstract: An Ethernet controller semiconductor chip has a system control unit, a media access control layer coupled with the system control unit, a physical layer coupled with the media access control layer, wherein the physical layer comprises a receiving port and a transmitting port, a switch control unit for providing a control signal for auto media device interface switching, and a plurality of external pins, wherein four pins are coupled with the receiving and transmitting port of the physical layer and one pin is coupled with the switch control unit for providing external access to the control signal for auto media device interface switching.

Abstract: A semiconductor integrated circuit device upon exiting from a low power mode, wakes up and re-initializes logic circuits so as to restore previous logic states of internal registers without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. Thus not distributing the operation of other devices connected to the semiconductor integrated circuit device previously in the low power mode. Once all internal logic and registers of the semiconductor integrated circuit device have been re-initialized, a “low power state wake-up and restore” signal may issue. This signal indicates that the I/O configuration control and data states stored in the I/O keeper cell at the time the integrated circuit device entered into the low power mode have been reinstated and control may be returned to the logic circuits and/or internal registers of the semiconductor integrated circuit device.

Abstract: A semiconductor integrated circuit device upon exiting from a low power mode, wakes up and re-initializes logic circuits so as to restore previous logic states of internal registers without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. Thus not distributing the operation of other devices connected to the semiconductor integrated circuit device previously in the low power mode. Once all internal logic and registers of the semiconductor integrated circuit device have been re-initialized, a “low power state wake-up and restore” signal may issue. This signal indicates that the I/O configuration control and data states stored in the I/O keeper cell at the time the integrated circuit device entered into the low power mode have been reinstated and control may be returned to the logic circuits and/or internal registers of the semiconductor integrated circuit device.

Abstract: The present invention relates to methods and apparatuses for providing data storage which can be completely erased to prevent access to previously stored data.

Abstract: A cable includes an inner conductor, an inner dielectric, and a guard conductor, where the inner dielectric is between the inner conductor and the guard conductor. The cable also includes an outer dielectric, and a shield conductor, where the outer dielectric is between the guard conductor and the shield conductor. The cable further includes an additional layer of material between the outer dielectric and the shield conductor of suitable composition for reducing triboelectric current generation between the outer dielectric and the shield conductor to less than that which would occur were the outer dielectric and the shield conductor to directly adjoin each other.

Abstract: An Ethernet controller semiconductor chip has a system control unit, a media access control layer coupled with the system control unit, a physical layer coupled with the media access control layer, wherein the physical layer comprises a receiving port and a transmitting port, a switch control unit for providing a control signal for auto media device interface switching, and a plurality of external pins, wherein four pins are coupled with the receiving and transmitting port of the physical layer and one pin is coupled with the switch control unit for providing external access to the control signal for auto media device interface switching.

Abstract: An Ethernet controller has a buffer memory for receiving data packets, a data flow control unit for controlling the data flow to Ethernet controller, a packet counter, packet counter control logic for incrementing and decrementing the packet counter, a first register for storing a watermark, and a comparator logic coupled to the packet counter and the register for sending control signals to the data flow control unit.

Abstract: A controller, in particular an Ethernet controller has a control unit operable to receive commands and data through an I/O interface; a plurality of registers arranged in a register block which is divided into a plurality of register banks, wherein at least one register controls a function of the controller; a register address unit having logic for accessing one of the plurality of registers by a plurality of addressing schemes, wherein the addressing schemes at least has a direct address provided by received data, a combined address provided by a partial address from a received command and a bank address stored in a bank register, and an address selected form a plurality of predetermined addresses through a received command.

Abstract: A controller has an interface, a buffer memory, a first set of registers for accessing the buffer memory, a second set of registers independent from the first set of registers for accessing the buffer memory, and a control unit for decoding and executing buffer memory access commands received by the interface to access the buffer memory through either the first or second set of registers.

Abstract: A semiconductor integrated circuit device uses two keeper cells per configuration and/or enable bit as dual redundant storage with error detection thereof. One of the two keeper cells stores a logic level and the other keeper cell stores the inverse of that logic level before the integrated circuit device goes into a low power mode. An exclusive OR (XOR) is performed on the outputs of the two keeper cells (a keeper cell pair) such that if the two keeper cells of the keeper cell pair do not have opposite logic levels stored therein, then the respective XOR outputs an error signal for that keeper cell pair and the error signal is used to force the integrated circuit device out of the low power mode, depending on software control, with or without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered.

Abstract: A semiconductor integrated circuit device upon exiting from a low power mode, wakes up and re-initializes logic circuits so as to restore previous logic states of internal registers without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. Thus not distributing the operation of other devices connected to the semiconductor integrated circuit device previously in the low power mode. Once all internal logic and registers of the semiconductor integrated circuit device have been re-initialized, a “low power state wake-up and restore” signal may issue. This signal indicates that the I/O configuration control and data states stored in the I/O keeper cell at the time the integrated circuit device entered into the low power mode have been reinstated and control may be returned to the logic circuits and/or internal registers of the semiconductor integrated circuit device.