Abstract: An Ethernet controller semiconductor chip has a system control unit, a media access control layer coupled with the system control unit, a physical layer coupled with the media access control layer, wherein the physical layer comprises a receiving port and a transmitting port, a switch control unit for providing a control signal for auto media device interface switching, and a plurality of external pins, wherein four pins are coupled with the receiving and transmitting port of the physical layer and one pin is coupled with the switch control unit for providing external access to the control signal for auto media device interface switching.

Abstract: A semiconductor integrated circuit device upon exiting from a low power mode, wakes up and re-initializes logic circuits so as to restore previous logic states of internal registers without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. Thus not distributing the operation of other devices connected to the semiconductor integrated circuit device previously in the low power mode. Once all internal logic and registers of the semiconductor integrated circuit device have been re-initialized, a “low power state wake-up and restore” signal may issue. This signal indicates that the I/O configuration control and data states stored in the I/O keeper cell at the time the integrated circuit device entered into the low power mode have been reinstated and control may be returned to the logic circuits and/or internal registers of the semiconductor integrated circuit device.

Abstract: A semiconductor integrated circuit device upon exiting from a low power mode, wakes up and re-initializes logic circuits so as to restore previous logic states of internal registers without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. Thus not distributing the operation of other devices connected to the semiconductor integrated circuit device previously in the low power mode. Once all internal logic and registers of the semiconductor integrated circuit device have been re-initialized, a “low power state wake-up and restore” signal may issue. This signal indicates that the I/O configuration control and data states stored in the I/O keeper cell at the time the integrated circuit device entered into the low power mode have been reinstated and control may be returned to the logic circuits and/or internal registers of the semiconductor integrated circuit device.

Abstract: The present invention relates to methods and apparatuses for providing data storage which can be completely erased to prevent access to previously stored data.

Abstract: A cable includes an inner conductor, an inner dielectric, and a guard conductor, where the inner dielectric is between the inner conductor and the guard conductor. The cable also includes an outer dielectric, and a shield conductor, where the outer dielectric is between the guard conductor and the shield conductor. The cable further includes an additional layer of material between the outer dielectric and the shield conductor of suitable composition for reducing triboelectric current generation between the outer dielectric and the shield conductor to less than that which would occur were the outer dielectric and the shield conductor to directly adjoin each other.

Abstract: An Ethernet controller semiconductor chip has a system control unit, a media access control layer coupled with the system control unit, a physical layer coupled with the media access control layer, wherein the physical layer comprises a receiving port and a transmitting port, a switch control unit for providing a control signal for auto media device interface switching, and a plurality of external pins, wherein four pins are coupled with the receiving and transmitting port of the physical layer and one pin is coupled with the switch control unit for providing external access to the control signal for auto media device interface switching.

Abstract: A controller, in particular an Ethernet controller has a control unit operable to receive commands and data through an I/O interface; a plurality of registers arranged in a register block which is divided into a plurality of register banks, wherein at least one register controls a function of the controller; a register address unit having logic for accessing one of the plurality of registers by a plurality of addressing schemes, wherein the addressing schemes at least has a direct address provided by received data, a combined address provided by a partial address from a received command and a bank address stored in a bank register, and an address selected form a plurality of predetermined addresses through a received command.

Abstract: An Ethernet controller has a buffer memory for receiving data packets, a data flow control unit for controlling the data flow to Ethernet controller, a packet counter, packet counter control logic for incrementing and decrementing the packet counter, a first register for storing a watermark, and a comparator logic coupled to the packet counter and the register for sending control signals to the data flow control unit.

Abstract: A controller has an interface, a buffer memory, a first set of registers for accessing the buffer memory, a second set of registers independent from the first set of registers for accessing the buffer memory, and a control unit for decoding and executing buffer memory access commands received by the interface to access the buffer memory through either the first or second set of registers.

Abstract: A semiconductor integrated circuit device uses two keeper cells per configuration and/or enable bit as dual redundant storage with error detection thereof. One of the two keeper cells stores a logic level and the other keeper cell stores the inverse of that logic level before the integrated circuit device goes into a low power mode. An exclusive OR (XOR) is performed on the outputs of the two keeper cells (a keeper cell pair) such that if the two keeper cells of the keeper cell pair do not have opposite logic levels stored therein, then the respective XOR outputs an error signal for that keeper cell pair and the error signal is used to force the integrated circuit device out of the low power mode, depending on software control, with or without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered.

Abstract: A semiconductor integrated circuit device upon exiting from a low power mode, wakes up and re-initializes logic circuits so as to restore previous logic states of internal registers without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. Thus not distributing the operation of other devices connected to the semiconductor integrated circuit device previously in the low power mode. Once all internal logic and registers of the semiconductor integrated circuit device have been re-initialized, a “low power state wake-up and restore” signal may issue. This signal indicates that the I/O configuration control and data states stored in the I/O keeper cell at the time the integrated circuit device entered into the low power mode have been reinstated and control may be returned to the logic circuits and/or internal registers of the semiconductor integrated circuit device.

Abstract: A semiconductor integrated circuit device upon exiting from a low power mode, wakes up and re-initializes logic circuits so as to restore previous logic states of internal registers without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. Thus not distributing the operation of other devices connected to the semiconductor integrated circuit device previously in the low power mode. Once all internal logic and registers of the semiconductor integrated circuit device have been re-initialized, a “low power state wake-up and restore” signal may issue. This signal indicates that the I/O configuration control and data states stored in the I/O keeper cell at the time the integrated circuit device entered into the low power mode have been reinstated and control may be returned to the logic circuits and/or internal registers of the semiconductor integrated circuit device.

Abstract: A cable includes an inner conductor, an inner dielectric, and a guard conductor, where the inner dielectric is between the inner conductor and the guard conductor. The cable also includes an outer dielectric, and a shield conductor, where the outer dielectric is between the guard conductor and the shield conductor. The cable further includes an additional layer of material between the outer dielectric and the shield conductor of suitable composition for reducing triboelectric current generation between the outer dielectric and the shield conductor to less than that which would occur were the outer dielectric and the shield conductor to directly adjoin each other.

Abstract: Containers, lids, and sleeve structures are disclosed. Particularly, sleeve structures configured for insulating, stabilizing, or both insulating and stabilizing a container are disclosed. Further, a sleeve structure including a plurality of circumferentially adjacent, longitudinally extending sections and a sleeve structure including one or more frustoconical regions are disclosed. Containers, lids, and sleeve structures including at least one stabilizing feature are disclosed. Assemblies including a lower container, associated lid and sleeve structure, wherein at least one of the lower container, the lid, or the sleeve structure includes at least one stabilizing feature for engaging at least a portion of a sleeve structure associated with an upper container, wherein the upper container is positioned longitudinally above and is substantially aligned or centered with respect to a lower container, are disclosed.

Abstract: A system provides for high level disinfection or sterilization of an endoscope having a first portion adapted for immersion and a second portion not adapted for immersion. The system includes a container having a first basin sized and adapted to receive the first portion of the endoscope for immersion, a separate and adjacent second basin sized and adapted to receive the second portion of the endoscope, a wall between the first basing and the second basin, and a trough in an upper portion of the wall between the first basin and second basin through which a tube connecting the first portion of the endoscope and the second portion of the endoscope may extend.

Abstract: A cable includes an inner conductor, an inner dielectric, and a guard conductor, where the inner dielectric is between the inner conductor and the guard conductor. The cable also includes an outer dielectric, and a shield conductor, where the outer dielectric is between the guard conductor and the shield conductor. The cable further includes an additional layer of material between the outer dielectric and the shield conductor of suitable composition for reducing triboelectric current generation between the outer dielectric and the shield conductor to less than that which would occur were the outer dielectric and the shield conductor to directly adjoin each other.

Abstract: A lid mechanism for a dishwasher having an least one washing unit provided with a lid includes at least one bracket that can be mounted to one of an outer support body and opposing side edge portions of a lid. The bracket includes a pin element that extends laterally outwardly from the bracket. The lid mechanism further includes at least one guide member that can be mounted to another of the outer support body and the opposing side edge portions of the lid. The guide member establishes a cam member and a guide track which cooperates with the pin element to raise and lower the lid relative to the washing unit. A spring is provided to biase the lid in a direction away from the washing unit.

Abstract: A cable includes an inner conductor, an inner dielectric, and a guard conductor, where the inner dielectric is between the inner conductor and the guard conductor. The cable also includes an outer dielectric, and a shield conductor, where the outer dielectric is between the guard conductor and the shield conductor. The cable further includes an additional layer of material between the outer dielectric and the shield conductor of suitable composition for reducing triboelectric current generation between the outer dielectric and the shield conductor to less than that which would occur were the outer dielectric and the shield conductor to directly adjoin each other.

Abstract: A cable includes an inner conductor, an inner dielectric, and a guard conductor, where the inner dielectric is between the inner conductor and the guard conductor. The cable also includes an outer dielectric, and a shield conductor, where the outer dielectric is between the guard conductor and the shield conductor. The cable further includes an additional layer of material between the outer dielectric and the shield conductor of suitable composition for reducing triboelectric current generation between the outer dielectric and the shield conductor to less than that which would occur were the outer dielectric and the shield conductor to directly adjoin each other.

Abstract: A vertical height adjustment mechanism for a dish rack includes a slide member fixedly mounted relative to a support member, a housing secured to the dish rack, and a latch member. The housing includes a central guide channel that slidably receives the slide member. The latch member includes a support leg, an actuating arm and an intermediate portion joining the support leg and actuating arm. The sliding element includes an end portion that receives and retains the support leg of the latch when the dish rack is in the raised position.