Abstract: An integrated circuit having an array of programmable processing elements and a memory interface linked by an on-chip communication network. Each processing element includes a plurality of processing cores and a local memory. The memory interface block is operably coupled to external memory and to the on-chip communication network. The memory interface supports accessing the external memory in response to messages communicated from the processing elements of the array over the on-chip communication network. A portion of the local memory for a plurality of the processing elements of the array as well as a portion of the external memory are both allocated to store data shared by a plurality of processing elements of the array during execution of programmed operations distributed thereon.

Abstract: An integrated circuit an array of nodes linked by an on-chip communication network. Messages are communicated between nodes utilizing logical channels representing hardware resources at the associated nodes. A given logical channel is associated with a receiver node and a transmitter node. The receiver node is adapted to send flow control messages to the transmitter node. The flow control messages include credits that identify hardware resources of the receiver node that are available for receiving messages over the given logical channel. The transmitter node is adapted to maintain a running total of the credits included as part of the flow control messages communicated from the receiver node and to initiate transmission of messages to the receiver node in accordance with the running total of credits maintained at the transmitter node.

Abstract: A system-on-chip integrated circuit (and multi-chip systems based thereon) that includes a bridge interface that provides transparent bridging of data communicated between integrated circuits.

Abstract: A system-on-chip integrated circuit (and multi-chip systems based thereon) that includes a bridge interface that employs data scrambling and error correction on data communicated between integrated circuits.

Abstract: An apparatus for fast failure switch over in an ETHERNET switch includes redundant switch (trunk) ports (a main and a backup) and hardware and software logic for redirecting traffic to the backup port when the main port (or the link associated with it) fails. The switchover is immediate and is based on the content of a local status register which indicates the port (link) status. Thus, frames addressed to the dead port are redirected to the backup port and few frames are lost. The STP function may proceed concurrently and eventually no more frames are addressed to the dead port.

Abstract: An apparatus for fast failure switch over in an ETHERNET switch includes redundant switch (trunk) ports (a main and a backup) and hardware and software logic for redirecting traffic to the backup port when the main port (or the link associated with it) fails. The switchover is immediate and is based on the content of a local status register which indicates the port (link) status. Thus, frames addressed to the dead port are redirected to the backup port and few frames are lost. The STP function may proceed concurrently and eventually no more frames are addressed to the dead port.