Abstract: A method and apparatus for testing and characterizing features formed on a substrate. In one embodiment, a test structure is provided that includes a test element having a first side and an opposing second side. A first set of one or more structures defining a first region having a first local density are disposed adjacent the first side of the test element. A second set of one or more structures defining a second region having a second local density are disposed adjacent the second side of the test element. A third set of one or more structures defining a third region having a first global density are disposed adjacent the first region. A fourth set of one or more structures defining a fourth region having a second global density are disposed adjacent the second region.

Abstract: The present invention provides methods of post-layout processing, such as OPC post-processing, through partitioning of integrated circuit data files. Partitioning methods of the present invention comprise forming partitioned identical cell groups. Each partitioned identical cell group comprises identical cells such that the cells within a partitioned group include identical cell data file components and identical cell proximity layout patterns. The partitioned cells of an identical cell group are then subjected to OPC post-processing. Non-partitioned cells can be subjected to OPC post-processing separately. In another method of the present invention an integrated circuit data file including at least one diagonal line, is rotated to obtain a rectilinear orientation of the line that was originally in a diagonal orientation. The line is subjected to OPC post-processing while in the rectilinear position. Thereafter, the data file is rotated in order to return the line to its original diagonal position.

Abstract: A method and apparatus for testing and characterizing features formed on a substrate. In one embodiment, a test structure is provided that includes a test element having a first side and an opposing second side. A first set of one or more structures defining a first region having a first local density are disposed adjacent the first side of the test element. A second set of one or more structures defining a second region having a second local density are disposed adjacent the second side of the test element. A third set of one or more structures defining a third region having a first global density are disposed adjacent the first region. A fourth set of one or more structures defining a fourth region having a second global density are disposed adjacent the second region.

Abstract: A semiconductor flash memory device with increased gate coupling ratio and a method of preparing this flash memory device. The semiconductor flash memory device includes a notched floating polysilicon gate. The notches are at the interface between the floating polysilicon layer and the tunneling dielectric layer. The notches reduce the capacitance between the floating polysilicon and the channel region. The reduced capacitance results in the increased gate coupling ratio. The degree of capacitance reduction, which affects the gate coupling ratio increase, is controlled by the width of the notches. The floating polysilicon gate etch includes a first anisotropic etch and a second isotropic etch. The widths of the notches are controlled by the etch time of the isotropic etch.

Abstract: A method and apparatus for reducing line edge roughness, comprising patterning a photoresist to define lines for etching an underlying layer, depositing a post development material between the lines, curing and removing the post development material to reduce line edge roughness, trimming the lines in the underlying layer, and then etching the underlying layer.

Abstract: The present invention generally provides an apparatus and a method for inspecting a substrate in a substrate processing system. In one aspect, a voltage or current source is used in conjunction with a power density receiving device, such as a spectrometer, to inspect a substrate for various noise spectrum signatures. In one embodiment, spectral data collected from a given substrate is used to generate a current or voltage spectral signature. This spectral signature may then be compared to a reference spectral density signature to predict reliability of a feature structure of a substrate in processing and feedback to the substrate processing system for substrate processing control. Embodiments of the invention further include computer-readable media containing instructions for controlling the substrate processing system, and computer program products having computer-readable program code embodied therein for controlling the substrate processing system and inspecting defects on semiconductor features.

Abstract: A semiconductor flash memory device with increased gate coupling ratio and a method of preparing this flash memory device. The semiconductor flash memory device includes a notched floating polysilicon gate. The notches are at the interface between the floating polysilicon layer and the tunneling dielectric layer. The notches reduce the capacitance between the floating polysilicon and the channel region. The reduced capacitance results in the increased gate coupling ratio. The degree of capacitance reduction, which affects the gate coupling ratio increase, is controlled by the width of the notches. The floating polysilicon gate etch includes a first anisotropic etch and a second isotropic etch. The widths of the notches are controlled by the etch time of the isotropic etch.

Abstract: A method is provided for processing and etching a substrate with a patterned photoresist layer on its surface. In one aspect, a method is provided for processing a substrate including illuminating a substrate with ultraviolet light, emitting a fluorescent light from the photoresist layer, measuring the intensity of the emitted fluorescent light and determining the open area percentage value for the patterned substrate. In another aspect, a method is provided for processing a substrate including providing the substrate, measuring the open area percentage value for the substrate, transmitting the open area percentage value to a processor, selecting an etch process for the substrate, transferring the substrate to a processing chamber, and etching the substrate.

Abstract: An improved I.sub.CCQ test method uses illumination of the integrated circuit to generate photo-induced currents and diode effects in order to detect types of circuits faults not otherwise detectable using conventional I.sub.CCQ testing methods.

Abstract: A transistor device 10 formed in a semiconductor layer 12 is disclosed herein. A first source/drain region 14 is formed in the semiconductor layer 12. A second source/drain region 16 is also formed in the semiconductor layer 12 and is spaced from the first source/drain region 14 by a channel region 18. The second source/drain region 16 includes (1) a lightly doped portion 16b adjacent the channel region 18 and abutting the top surface, (2) a main portion 16a abutting the top surface and spaced from the channel region 18 by the lightly doped portion 16b, and (3) a deep portion 16c formed within the layer 12 and spaced from the top surface by the lightly doped portion 16b and the main portion 16a. A gate electrode 20 is formed over at least a portion of the channel region 18 and insulated therefrom.