Abstract: An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to a test mode selection. The first transceiver receives the test data sequence from the test sequence generator and is configured in a loopback mode to transmit and receive the test data sequence. The second transceiver receives the test data sequence received by the first transceiver and is configured in a loopback mode to transmit and receive the test data sequence. The test sequence analyzer determines whether the test data sequence received by the second transceiver matches the test data sequence generated by the test sequence generator.

Abstract: A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A detector coupled to the first interface detects the OOB information. An encoder coupled to the detector encodes the OOB information into one or more symbols (e.g., control characters). A second interface is coupled to the encoder and a second communication link (e.g., a serial transport path). The second interface transmits the symbols on the second communication link. The device also includes mechanisms for preventing false presence detection of terminating devices.

Abstract: An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to a test mode selection. The first transceiver receives the test data sequence from the test sequence generator and is configured in a loopback mode to transmit and receive the test data sequence. The second transceiver receives the test data sequence received by the first transceiver and is configured in a loopback mode to transmit and receive the test data sequence. The test sequence analyzer determines whether the test data sequence received by the second transceiver matches the test data sequence generated by the test sequence generator.

Abstract: An integrated circuit includes clock synthesis and distribution circuitry that includes cascaded PLLs to deliver low-noise transmit and receive clock signals that can be tuned over a broad range of frequencies. The clock synthesis circuitry derives a low-jitter intermediate reference clock signal IRClk from a relatively noisy, low-frequency external reference clock signal using a first PLL stage with a high-Q voltage-controlled oscillator (VCO). This first PLL stage has a low loop bandwidth, and thus acts as a low-pass filter (LPF) to remove the reference clock jitter. The low jitter intermediate clock signal is distributed to one or more second PLL stages that derive higher frequency transmit and/or receive clock signals from the intermediate clock signal. Each second PLL stage includes a low-Q VCO that exhibits a considerable tuning range to support a number of transmit and receive data rates.