Abstract: A data link includes a transmit side having a physical layer circuit including a serial pin interface and a data link circuit layer coupled by one or more parallel multi-bit data lanes to the physical layer circuit. The data link layer circuit transfers parallel data to the physical layer circuit responsive to a parallel clock signal. The data link layer circuit includes a pseudo-random bit sequence generator circuit configured to generate, based on the parallel clock signal, a pseudo-random bit sequence having a width of M bits, where M is greater than 1. The data link layer circuit further includes a hold circuit coupled to receive and hold the pseudo-random bit sequence for a selected number of cycles of the parallel clock signal determined by a hold signal and a timing circuit configured to assert the hold signal based on multiple cycles of the parallel clock signal.

Abstract: In some implementations, the operations of a software system may include the execution of untrusted device drivers. The execution of an untrusted device driver may be initiated when an untrusted device driver that is a set of executable instructions is obtained. A computing resource for the execution of the device driver may be further determined from a device-driver manifest of the untrusted device driver. Computing resources may include one or more of a hardware resource, a memory, an input/output port, an interrupt request line, and an inter-process communication channel. Trusted local access objects may be used by the untrusted device driver to access the computing resources.

Abstract: Described herein are one or more implementations for describing and/or addressing the configuration requirements of applications, extensions, device drivers, and other components of a software system.

Abstract: An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat.