Abstract: Robotic systems for orthopedic surgery are provided. The robotic systems may include at least first and second motors coupled to each other. An output shaft of one of the motors may be connectable to a surgical tool guide. An output shaft of another of the motors may be coupled to a portion of a ball and socket joint. A corresponding portion of the ball and socket joint may be coupled to a bone mount which may be attached to a bone to mount the first and second motors to bone for performing orthopedic surgical procedures.

Abstract: A Marx generator has at least two branches for providing a Marx voltage at an output pole. Each of the branches has a plurality of capacitor stages with voltage poles, cross branches with spark gaps, a last capacitor stage at its output end, and a first capacitor stage connected to an operating voltage. The branches have a common triggering section with a common first capacitor stage, a first adjacent cross branch, and an input pole. Each of the branches has the triggering section and also an individual portion with at least one capacitor stage that is only associated with the branch. A resonator arrangement contains the Marx generator and resonators at the respective output poles of the branches. A radiation arrangement has the resonator arrangement and a multi-feed waveguide with at least two of the resonators for respectively feeding an electromagnetic wave.

Abstract: A broadband transition coupling for transition between a waveguide and a printed circuit board with a substrate integrated waveguide is disclosed. The broadband transition coupling comprises a main body that encompasses an air-filled waveguide section and a transition section. The air-filled waveguide section comprises a first interface for the waveguide. The transition section provides a second interface for the printed circuit board. The transition section continuously tapers along the second interface in order to reduce a height of the transition section for transition coupling with the printed circuit board. Further, the present disclosure relates to a broadband system for processing electromagnetic signals.

Abstract: A broadband transition coupling for transition between a waveguide and a printed circuit board with a substrate integrated waveguide is disclosed. The broadband transition coupling comprises a main body that encompasses an air-filled waveguide section and a transition section. The air-filled waveguide section comprises a first interface for the waveguide. The transition section provides a second interface for the printed circuit board. The transition section continuously tapers along the second interface in order to reduce a height of the transition section for transition coupling with the printed circuit board. Further, the present disclosure relates to a broadband system for processing electromagnetic signals.

Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for hardware acceleration are presented. A plurality of computational nodes for processing data is provided, each node performing a corresponding operation for data received at that node. A metric module is used to determine a compression benefit metric pertaining to performance of the corresponding operations of one or more computational nodes with recompressed data. An accelerator module recompresses data for processing by the one or more computational nodes based on the compression benefit metric indicating a benefit gained by using the recompressed data. A distribution function may be used to distribute data among a plurality of nodes.

Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for hardware acceleration are presented. A plurality of computational nodes for processing data is provided, each node performing a corresponding operation for data received at that node. A metric module is used to determine a compression benefit metric pertaining to performance of the corresponding operations of one or more computational nodes with recompressed data. An accelerator module recompresses data for processing by the one or more computational nodes based on the compression benefit metric indicating a benefit gained by using the recompressed data. A distribution function may be used to distribute data among a plurality of nodes.

Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for hardware acceleration are presented. A plurality of computational nodes for processing data is provided, each node performing a corresponding operation for data received at that node. A metric module is used to determine a compression benefit metric pertaining to performance of the corresponding operations of one or more computational nodes with recompressed data. An accelerator module recompresses data for processing by the one or more computational nodes based on the compression benefit metric indicating a benefit gained by using the recompressed data. A distribution function may be used to distribute data among a plurality of nodes.

Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for hardware acceleration are presented. A plurality of computational nodes for processing data is provided, each node performing a corresponding operation for data received at that node. A metric module is used to determine a compression benefit metric pertaining to performance of the corresponding operations of one or more computational nodes with recompressed data. An accelerator module recompresses data for processing by the one or more computational nodes based on the compression benefit metric indicating a benefit gained by using the recompressed data. A distribution function may be used to distribute data among a plurality of nodes.

Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for hardware acceleration are presented. A plurality of computational nodes for processing data is provided, each node performing a corresponding operation for data received at that node. A metric module is used to determine a compression benefit metric pertaining to performance of the corresponding operations of one or more computational nodes with recompressed data. An accelerator module recompresses data for processing by the one or more computational nodes based on the compression benefit metric indicating a benefit gained by using the recompressed data. A distribution function may be used to distribute data among a plurality of nodes.

Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for hardware acceleration are presented. A plurality of computational nodes for processing data is provided, each node performing a corresponding operation for data received at that node, A metric module is used to determine a compression benefit metric pertaining to performance of the corresponding operations of one or more computational nodes with recompressed data, An accelerator module recompresses data for processing by the one or more computational nodes based on the compression benefit metric indicating a benefit gained by using the recompressed data. A distribution function may be used to distribute data among a plurality of nodes.

Abstract: An approach for providing compression of a database table that uses a compiled table algorithm (CTA) that provides leverage. Data within any given column in adjacent rows is often the same as or closely related to its neighbors. Rather than storing data in each column of each row as a specific integer, floating point, or character data value, a field reconstruction instruction is stored that when executed by a decompression engine can reconstruct the data value. The field reconstruction instruction may be bit granular and may depend upon past history given that the data compression engine may preserve state as row data is streamed off a storage device.

Abstract: A programmable streaming data processor that can be programmed to recognize record and field structures of data received from a streaming data source such as a mass storage device. Being programmed with, for example, field information, the unit can locate record and field boundaries and employ logical arithmetic methods to compare fields with one another or with values otherwise supplied by general purpose processors to precisely determine which records are worth transferring to memory of the more general purpose distributed processors. The remaining records arrive and are discarded by the streaming data processor or are tagged with status bits to indicate to the more general purpose processor that they are to be ignored. In a preferred embodiment, the streaming data processor may analyze and discard records for several reasons. The first reason may be an analysis of contents of the field.

Abstract: An approach for providing compression of a database table that uses a compiled table algorithm (CTA) that provides leverage. Data within any given column in adjacent rows is often the same as or closely related to its neighbors. Rather than storing data in each column of each row as a specific integer, floating point, or character data value, a field reconstruction instruction is stored that when executed by a decompression engine can reconstruct the data value. The field reconstruction instruction may be bit granular and may depend upon past history given that the data compression engine may preserve state as row data is streamed off a storage device.

Abstract: A programmable streaming data processor that can be programmed to recognize record and field structures of data received from a streaming data source such as a mass storage device. Being programmed with, for example, field information, the unit can locate record and field boundaries and employ logical arithmetic methods to compare fields with one another or with values otherwise supplied by general purpose processors to precisely determine which records are worth transferring to memory of the more general purpose distributed processors. The remaining records arrive and are discarded by the streaming data processor or are tagged with status bits to indicate to the more general purpose processor that they are to be ignored. In a preferred embodiment, the streaming data processor may analyze and discard records for several reasons. The first reason may be an analysis of contents of the field.

Abstract: Random access to arbitrary fields of a video segment compressed using both interframe and intraframe techniques is enhanced by adding state information to the bitstream prior to each intraframe compressed image to allow each intraframe compressed image to be randomly accessed, by generating a field index that maps each temporal field to the offset in the compressed bitstream of the data used to decode the field, and by playing back segments using two or more alternatingly used decoders. The cut density may be improved by eliminating from the bitstream applied to each decoder any data corresponding to bidirectionally compressed images that would otherwise be used by the decoder to generate fields prior to the desired field.

Abstract: Random access to arbitrary fields of a video segment compressed using both interframe and intraframe techniques is enhanced by adding state information to the bitstream prior to each intraframe compressed image to allow each intraframe compressed image to be randomly accessed, by generating a field index that maps each temporal field to the offset in the compressed bitstream of the data used to decode the field, and by playing back segments using two or more alternatingly used decoders. The cut density may be improved by eliminating from the bitstream applied to each decoder any data corresponding to bidirectionally compressed images that would otherwise be used by the decoder to generate fields prior to the desired field.

Abstract: Random access to arbitrary fields of a video segment compressed using both interframe and intraframe techniques is enhanced by adding state information to the bitstream prior to each intraframe compressed image to allow each intraframe compressed image to be randomly accessed by generating a field index that maps each temporal field to the offset in the compressed bitstream of the data used to decode the field, and by playing back segments using two or more alternatingly used decoders. The cut density may be improved by eliminating from the bitstream applied to each decoder any data corresponding to bidirectionally compressed images that would otherwise be used by the decoder to generate fields prior to the desired field.

Abstract: A digital motion video processing circuit can capture, playback and manipulate digital motion video information using the system memory of a computer as a data buffer for holding compressed video data from the circuit. The system memory may be accessed by the circuit over a standard bus. A controller in the circuit directs data flow between an input/output port which transfer a stream of pixel data and to the standard bus. The controller directs data to and from either the standard bus or the input/output port through processing circuitry for compression, decompression, scaling and buffering. The standard bus may be a peripheral component interconnect (PCI) bus. The motion video processing circuit has a data path including pixel data and timing data indicative of a size of an image defined by the pixel data. The timing data is used and/or generated by each component which processes the pixel data, thereby enabling each component to process the pixel data without prior knowledge of the image format.

Abstract: A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency.

Abstract: A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency.