Abstract: Deep learning inference for imaging systems includes an imaging device comprising an image capture component and a vision processing unit configured to process the image through a first trained inference network to determine a first inference result. A host system trains a neural network for image classification and produces and transmits the first trained inference network to the vision processing unit of the imaging device. The first trained inference network provides stand-alone image classification, an object detection and/or a confidence score to the imaging device. The vision processing unit may further comprise a two or more trained inference networks configured to receive an inference result as an input and output a second inference result. A stereo camera system uses features and/or results from one or more inference network to control processing of three-dimensional data for the detected object.

Abstract: A method of soldering a semiconductor chip to a chip carrier includes arranging a solder deposit including solder and solder flux between a contact portion of the carrier and a contact portion of a chip pad arranged at a surface of the semiconductor chip. Arranging a dielectric layer at the surface of the semiconductor chip. The dielectric layer includes an opening within which the contact portion of the chip pad is exposed. The dielectric layer further includes arranging a solder flux outgassing trench separate from the opening and intersecting with the solder deposit. The method further includes melting the solder deposit which causes liquid solder to be moved over the solder flux outgassing trench for extraction of flux gas.

Abstract: A method for producing a semiconductor arrangement includes applying a metallization layer on an upper main side of a lower semiconductor chip, structuring the metallization layer, and fastening an upper semiconductor chip on the upper main side of the lower semiconductor chip by a bonding material, wherein the metallization layer is structured such that the metallization layer has an increased roughness along a contour of the upper semiconductor chip in comparison with the rest of the metallization layer, wherein wetting of the upper main side of the lower semiconductor chip by the bonding material is limited by a structure in the metallization layer to a region below the upper semiconductor chip.

Abstract: In an embodiment, a method comprises: obtaining input data including a plurality of parameters related to an energy system design; reducing the input data to a subset of the input data; in a first stage: feeding the subset of input data into a reduced version of a model for estimating an energy system configuration; estimating, using the reduced version of the model, a first energy system configuration and a lower bound solution for the first energy system configuration based on the subset of input data; and in a second stage following the first stage: feeding the input data and the lower bound solution into a full version of the model; and estimating, using the full version of the model, a second energy system configuration based on the input data and the lower bound solution.

Abstract: A method of soldering a semiconductor chip to a chip carrier includes arranging a solder deposit including solder and solder flux between a contact portion of the carrier and a contact portion of a chip pad arranged at a surface of the semiconductor chip. Arranging a dielectric layer at the surface of the semiconductor chip. The dielectric layer includes an opening within which the contact portion of the chip pad is exposed. The dielectric layer further includes arranging a solder flux outgassing trench separate from the opening and intersecting with the solder deposit. The method further includes melting the solder deposit which causes liquid solder to be moved over the solder flux outgassing trench for extraction of flux gas.

Abstract: A semiconductor package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, and a metal sheet having a first sheet surface and an opposite second sheet surface. The first sheet surface is exposed at the encapsulation body. The semiconductor chip is arranged at the second sheet surface. The first sheet surface has a pattern having first subdivisions having a first average roughness and second subdivisions having a second average roughness. The first average roughness is greater than the second average roughness.

Abstract: A clip, a semiconductor package, and a method are disclosed. In one example the clip includes a die attach portion having a first main face and a second main face opposite to the first main face, and at least one through-hole extending between the first and second main faces and including a curved transition from an inner wall of the at least one through-hole to the first main face.

Abstract: A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.

Abstract: A machine learning based multiyear projection planning for energy systems is disclosed. In some embodiments, a method comprises: obtaining input data for an energy system; determining one or more projection factors based on the input data; determining, based on a machine learning model, an operation or investment associated with the energy system to achieve lower cost or improve one or more metrics of the energy system for the multiyear horizon based at least in part on the one or more projection factors and a description of technology or infrastructure of the energy system; generating a recommended operation or investment decision for the energy system based at least in part on output of the machine learning model; and storing the recommended operation or investment decision.

Abstract: An electronic device and method is disclosed. In one example, the electronic device includes a solderable surface and at least one surface opening arranged in the solderable surface. The electronic device further includes an encapsulation material, encapsulating at least one electronic component of the electronic device, and at least one vent opening arranged in an area of the surface opening and extending through the encapsulation material.

Abstract: A semiconductor chip includes a chip pad arranged at a surface of the semiconductor chip. A dielectric layer is arranged at the surface of the semiconductor chip. The dielectric layer has an opening within which a contact portion of the chip pad is exposed, the opening having at least one straight side. The dielectric layer includes a solder flux outgassing trench arranged separate from and in the vicinity of the at least one straight side of the opening and that extends laterally beyond sides of the opening adjoining the straight side.

Abstract: Systems, methods and non-transitory computer-readable storage mediums are disclosed for cloud computing engineering, solar PV (SPV) or solar PV with storage (SPV/S) system configuration, pricing, quoting, advertising messaging, sales lead generation, and content marketing.

Abstract: The embodiments disclosed in this document are directed to an AI-enabled microgrid and DER planning platform that uses AI methods and takes into account cost calculations, emission calculations, technology investments and operation. In an embodiment, the computing platform is deployed on a network (cloud computing platform) that can be accessed by a variety of stakeholders (e.g., investors, technology vendors, energy providers, regulatory authorities). In an embodiment, the planning platform implements machine learning (e.g., neural networks) to estimate various planning parameters, where the neural networks are trained on observed data from real-world microgrid/minigrid and DER projects.

Abstract: A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste that reflowed to form the soldered joint. Corresponding methods of production are also described.

Abstract: A leadframe for flip chip attaching a semiconductor die thereon includes a rectangular area segmented into individual pads, the individual pads including a first pad, a second pad, and a third pad, wherein the first pad is larger than the second pad and larger than the third pad, and the second pad is located in a first corner area of the rectangular area and the third pad is located in a second corner area of the rectangular area, the second corner area being located diagonally opposite to the first corner area.

Abstract: A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste that reflowed to form the soldered joint. Corresponding methods of production are also described.

Abstract: The disclosed embodiments combine an energy balance (e.g., averaged energy profiles) with original time series data having smaller time steps to establish an energy balance (e.g., averaged profiles) and a power balance (e.g., smaller time step with original time series data) for a Distributed Energy Resources (DER), microgrid, or other energy system. In an embodiment, a method comprises: solving, with at least one processor, a first optimization problem on time series data related to energy system planning, the first optimization including applying a power balancing framework to the time series data that captures intra-hour variability; and selecting, with the at least one processor, technology assets and sizing for the energy system based on an average hourly and sub-hourly datasets.

Abstract: A passenger compartment which has a first connection device, by which the passenger compartment can be coupled to an aircraft, and a second connection device, by which the passenger compartment can be coupled to a land vehicle. The passenger compartment has an electrical circuit with an electrical energy storage. The electrical circuit of the passenger compartment has a coupling device by which electrical energy can be input from the electrical energy storage into an electrical circuit of the aircraft. The electrical circuit of the passenger compartment has a further coupling device by which electrical energy can be input from the electrical energy storage into an electrical circuit of the land vehicle.

Abstract: A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste reflowed to form the soldered joint. Corresponding methods of production are also described.

Abstract: A semiconductor arrangement includes a lower semiconductor chip, an upper semiconductor chip arranged over an upper main side of the lower semiconductor chip, a metallization layer arranged on the upper main side of the lower semiconductor chip, and a bonding material which fastens the upper semiconductor chip on the lower semiconductor chip. The metallization layer includes a structure with increased roughness in comparison with the rest of the metallization layer, the structure being arranged along a contour of the upper semiconductor chip.