Abstract: A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.

Abstract: A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.

Abstract: A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.

Abstract: A digital multilevel non-volatile memory integrated system includes an apparatus and method for high voltage, high precision pulsing generation. A voltage generator includes a low voltage high speed generator, a low voltage to high voltage high speed level translator, and a high voltage driver. A precise and stable high voltage level is attained across power supply, process, or temperature variation. The power may be optimized at the high voltage supply as tradeoff with power in the low voltage supply. A ping-pong operation sets up a high voltage level and the high voltage pulsing is output in a ping-pong fashion. A slew rate control circuit slows the input to achieve faster settling times. The high voltage is shaped by low voltage switching, HV fast switching and ramp circuit control. The high voltage pulsing may be fast and precise to permit real time control of the pulse parameters to adapt to memory cell attributes.

Abstract: A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.

Abstract: A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.

Abstract: A digital multilevel non-volatile memory integrated system includes an apparatus and method for high voltage, high precision pulsing generation. A voltage generator includes a low voltage high speed level generator, a low voltage to high voltage high speed level translator, and a high voltage driver. A precise and stable high voltage level is attained across power supply, process, or temperature variation. The power may be optimized at the high voltage supply as tradeoff with power in the low voltage supply. A ping-pong operation sets up a high voltage level and the high voltage pulsing is output in a ping-pong fashion. A slew rate control circuit slows the input step voltage to achieve faster settling times. The high voltage is shaped by low voltage switching, HV fast switching and ramp circuit control. The high voltage pulsing may be fast and precise to permit real time control of the pulse parameters to adapt to memory cell attributes.