Abstract: Embodiments relate to a system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes establishing a temporal interval that includes a plurality of temporal periods and an interval energy target for one or more processor cores. The method also includes determining for each temporal period a period energy target for the processor cores and determining a processor core throttling state for the processor cores. The method further includes adjusting the respective period energy target and the respective processor core throttling state at the beginning of each successive temporal period. The method also includes converging, subject to the adjusting, as each respective temporal period of the plurality of temporal periods is concluded, a total period energy consumption of the processor cores with the interval energy target.

Abstract: A system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes translating each activity level of the one or more processor cores to a respective charge value. The method also includes generating, at least partially subject to each translated charge value, one or more charge replenishment requests associated with the one or more processor cores. The method further includes transmitting the one or more charge replenishment requests to a pending queue prior to a delay queue.

Abstract: A system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes translating each activity level of the one or more processor cores to a respective charge value. The method also includes generating, at least partially subject to each translated charge value, one or more charge replenishment requests associated with the one or more processor cores. The method further includes transmitting the one or more charge replenishment requests to a pending queue prior to a delay queue.

Abstract: Aspects of the invention include monitoring code coverage by executing a code sequence having a plurality of embedded markers. Aspects also include transmitting, upon encountering one of the plurality of embedded markers, a probing signal corresponding to the one of the plurality of embedded markers. Aspects further include obtaining, by a programmable data recorder, a debug level for the execution of the code sequence. Aspects also include storing the probing signal in a trace array based on a determination, by a programmable data recorder based on the debug level, that the probing signal should be recorded.

Abstract: A system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes recording an activity level of one or more processor cores within a multicore processing device and translating each activity level of the one or more processor cores to a respective charge value. The method also includes generating, at least partially subject to each translated charge value, one or more charge replenishment requests associated with the one or more processor cores. The method further includes determining the one or more charge replenishment requests exceeds a power delivery capacity to the multicore processing device. The method also includes regulating the processing activity of the one or more processor cores to decrease a power consumption for the one or more processing cores.

Abstract: Providing deterministic frequency and voltage enhancements for a processor is disclosed. In an embodiment, a microcontroller on a processor identifies a plurality of parameters related to a processor, the plurality of parameters including at least a current supplied to the processor; determines, in dependence upon the plurality of parameters, one or more frequency scaling indexes including determining an effective switching capacitance ratio; identifies, in dependence upon the one or more frequency scaling indexes, a predetermined frequency parameter for the processor; and transitions, based on the frequency parameter, the processor to a target clock frequency.

Abstract: A system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes recording an activity level of one or more processor cores within a multicore processing device and translating each activity level of the one or more processor cores to a respective charge value. The method also includes generating, at least partially subject to each translated charge value, one or more charge replenishment requests associated with the one or more processor cores. The method further includes determining the one or more charge replenishment requests exceeds a power delivery capacity to the multicore processing device. The method also includes regulating the processing activity of the one or more processor cores to decrease a power consumption for the one or more processing cores.

Abstract: Embodiments relate to a system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes establishing a temporal interval that includes a plurality of temporal periods and an interval energy target for one or more processor cores. The method also includes determining for each temporal period a period energy target for the processor cores and determining a processor core throttling state for the processor cores. The method further includes adjusting the respective period energy target and the respective processor core throttling state at the beginning of each successive temporal period. The method also includes converging, subject to the adjusting, as each respective temporal period of the plurality of temporal periods is concluded, a total period energy consumption of the processor cores with the interval energy target.

Abstract: A method for managing a processor, the processor comprising a common supply rail and processor cores being connected to the common supply rail, wherein each processor core comprises a core unit, wherein the method comprises detecting idle state exits indicated by the core units; and delaying a command execution of at least one of the core units indicating an idle state exit when the number of idle state exits exceeds a predetermined threshold idle state exit number may reduce voltage droops due to several processor cores leaving the idle state at the same time.

Abstract: A critical path monitor (CPM) having a set of split paths is configured in an integrated circuit (IC) that includes a corresponding set of critical paths. A first and a second split path is configured with a first and a second simulated delay sections and fine delay sections, respectively. A delay of each of the first and second fine delay sections is adjustable in several steps. The delay of the first fine delay section is adjustable differently from the delay of the second fine delay section in response to a common operating condition change. Differently adjusting the delays of the first and the second fine delay sections causes an edge of a pulse to be synchronized between a first edge detector located after the first simulated delay section and a second edge detector located after the second simulated delay section.

Abstract: A method for managing a processor, the processor comprising a common supply rail and processor cores being connected to the common supply rail, wherein each processor core comprises a core unit, wherein the method comprises detecting idle state exits indicated by the core units; and delaying a command execution of at least one of the core units indicating an idle state exit when the number of idle state exits exceeds a predetermined threshold idle state exit number may reduce voltage droops due to several processor cores leaving the idle state at the same time.

Abstract: A critical path monitor (CPM) having a set of split paths is configured in an integrated circuit (IC) that includes a corresponding set of critical paths. A first and a second split path is configured with a first and a second simulated delay sections and fine delay sections, respectively. A delay of each of the first and second fine delay sections is adjustable in several steps. The delay of the first fine delay section is adjustable differently from the delay of the second fine delay section in response to a common operating condition change. Differently adjusting the delays of the first and the second fine delay sections causes an edge of a pulse to be synchronized between a first edge detector located after the first simulated delay section and a second edge detector located after the second simulated delay section.

Abstract: Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.

Abstract: A critical path monitor (CPM) is configured in an integrated circuit (IC). The IC includes a set of critical paths. The CPM includes a set of split paths, a split path in the set of split paths corresponding to a critical path in the set of critical paths, and a split path in the set of split paths including an edge detector. The edge detector is configured with a set of edge detector latches. A set of set-reset (SR) latches is configured such that an edge detector latch is associated with a corresponding SR latch. A reset signal is configured to reach the set of edge detector latches in an offset synchronization with a latch clock signal used in the set of edge detector latches. The CPM is configured to operate using a frequency of the latch clock signal such that the frequency is higher than a threshold frequency.

Abstract: The embodiments provide an assigned counter of a first set of counters and stores a value for an activity of a set of activities forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. A power manager manages the first set of counters, receives a set of activities to be monitored for a unit, groups the portion into subsets based on at least one of a frequency of occurrence of each activity and power consumption for each activity, sums the stored values corresponding to each activity in each subset to reach a total value for each subset, multiplies the total value of each subset by factor corresponding to the subset to form a scaled value for each subset, and sums the scaled value of each subset to form a power usage value.

Abstract: Illustrative embodiments estimate power consumption within a multi-core microprocessor chip. An authorized user selects a set of activities to be monitored. A value for each activity of the set of activities is stored in a separate counter of a set of counters, forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. The set of activities are grouped into subsets. The stored values corresponding to each activity in each subset are summed, forming a total value for each subset. The total value of each subset is multiplied by a factor corresponding to the subset, forming a scaled value for each subset. The scaled value of each subset is summed, forming a power usage value. A power manager adjusts the operational parameters of the unit based on a comparison of the power usage value to a threshold value.

Abstract: The illustrative embodiments described herein provide a computer-implemented method, apparatus, and a system for managing instructions. A load/store unit receives a first instruction at a port. The load/store unit rejects the first instruction in response to determining that the first instruction has a first reject condition. Then, the instruction sequencing unit activates a first bit in response to the load/store unit rejection the first instruction. The instruction sequencing unit blocks the first instruction from reissue while the first bit is activated. The processor unit determines a class of rejection of the first instruction. The instruction sequencing unit starts a timer. The length of the timer is based on the class of rejection of the first instruction. The instruction sequencing unit resets the first bit in response to the timer expiring. The instruction sequencing unit allows the first instruction to become eligible for reissue in response to resetting the first bit.

Abstract: A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.

Abstract: Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.

Abstract: Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.