Patents by Inventor Michael Stephen Floyd

Michael Stephen Floyd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9811150
    Abstract: A method for managing a processor, the processor comprising a common supply rail and processor cores being connected to the common supply rail, wherein each processor core comprises a core unit, wherein the method comprises detecting idle state exits indicated by the core units; and delaying a command execution of at least one of the core units indicating an idle state exit when the number of idle state exits exceeds a predetermined threshold idle state exit number may reduce voltage droops due to several processor cores leaving the idle state at the same time.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: November 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Alan James Drake, Michael Stephen Floyd, Charles Robert Lefurgy, Karthick Rajamani, Tobias Webel
  • Patent number: 9369119
    Abstract: A critical path monitor (CPM) having a set of split paths is configured in an integrated circuit (IC) that includes a corresponding set of critical paths. A first and a second split path is configured with a first and a second simulated delay sections and fine delay sections, respectively. A delay of each of the first and second fine delay sections is adjustable in several steps. The delay of the first fine delay section is adjustable differently from the delay of the second fine delay section in response to a common operating condition change. Differently adjusting the delays of the first and the second fine delay sections causes an edge of a pulse to be synchronized between a first edge detector located after the first simulated delay section and a second edge detector located after the second simulated delay section.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: June 14, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Alan James Drake, Michael Stephen Floyd, Pawel Owczarczyk, Gregory Scott Still, Marshall Dale Tiner, Xiaobin Yuan
  • Publication number: 20160132096
    Abstract: A method for managing a processor, the processor comprising a common supply rail and processor cores being connected to the common supply rail, wherein each processor core comprises a core unit, wherein the method comprises detecting idle state exits indicated by the core units; and delaying a command execution of at least one of the core units indicating an idle state exit when the number of idle state exits exceeds a predetermined threshold idle state exit number may reduce voltage droops due to several processor cores leaving the idle state at the same time.
    Type: Application
    Filed: November 10, 2015
    Publication date: May 12, 2016
    Inventors: Malcolm S. ALLEN-WARE, Alan James DRAKE, Michael Stephen FLOYD, Charles Robert LEFURGY, Karthick RAJAMANI, Tobias WEBEL
  • Publication number: 20150109043
    Abstract: A critical path monitor (CPM) having a set of split paths is configured in an integrated circuit (IC) that includes a corresponding set of critical paths. A first and a second split path is configured with a first and a second simulated delay sections and fine delay sections, respectively. A delay of each of the first and second fine delay sections is adjustable in several steps. The delay of the first fine delay section is adjustable differently from the delay of the second fine delay section in response to a common operating condition change. Differently adjusting the delays of the first and the second fine delay sections causes an edge of a pulse to be synchronized between a first edge detector located after the first simulated delay section and a second edge detector located after the second simulated delay section.
    Type: Application
    Filed: October 21, 2013
    Publication date: April 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: Alan James Drake, Michael Stephen Floyd, Pawel Owczarczyk, Gregory Scott Still, Marshall Dale Tiner, Xiaobin Yuan
  • Patent number: 9003417
    Abstract: Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: William Joseph Armstrong, Michael Stephen Floyd, Ronald Nick Kalla, Larry Scott Leitner, Balaram Sinharoy
  • Patent number: 8941426
    Abstract: A critical path monitor (CPM) is configured in an integrated circuit (IC). The IC includes a set of critical paths. The CPM includes a set of split paths, a split path in the set of split paths corresponding to a critical path in the set of critical paths, and a split path in the set of split paths including an edge detector. The edge detector is configured with a set of edge detector latches. A set of set-reset (SR) latches is configured such that an edge detector latch is associated with a corresponding SR latch. A reset signal is configured to reach the set of edge detector latches in an offset synchronization with a latch clock signal used in the set of edge detector latches. The CPM is configured to operate using a frequency of the latch clock signal such that the frequency is higher than a threshold frequency.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alan James Drake, Michael Stephen Floyd, Pawel Owczarczyk, Gregory Scott Still, Marshall Dale Tiner, Xiaobin Yuan
  • Patent number: 8650413
    Abstract: The embodiments provide an assigned counter of a first set of counters and stores a value for an activity of a set of activities forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. A power manager manages the first set of counters, receives a set of activities to be monitored for a unit, groups the portion into subsets based on at least one of a frequency of occurrence of each activity and power consumption for each activity, sums the stored values corresponding to each activity in each subset to reach a total value for each subset, multiplies the total value of each subset by factor corresponding to the subset to form a scaled value for each subset, and sums the scaled value of each subset to form a power usage value.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Michael Stephen Floyd, Maria Lorena Pesantez
  • Patent number: 8271765
    Abstract: The illustrative embodiments described herein provide a computer-implemented method, apparatus, and a system for managing instructions. A load/store unit receives a first instruction at a port. The load/store unit rejects the first instruction in response to determining that the first instruction has a first reject condition. Then, the instruction sequencing unit activates a first bit in response to the load/store unit rejection the first instruction. The instruction sequencing unit blocks the first instruction from reissue while the first bit is activated. The processor unit determines a class of rejection of the first instruction. The instruction sequencing unit starts a timer. The length of the timer is based on the class of rejection of the first instruction. The instruction sequencing unit resets the first bit in response to the timer expiring. The instruction sequencing unit allows the first instruction to become eligible for reissue in response to resetting the first bit.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Michael Stephen Floyd, Dung Quoc Nguyen, Bruce Joseph Ronchetti
  • Patent number: 8271809
    Abstract: Illustrative embodiments estimate power consumption within a multi-core microprocessor chip. An authorized user selects a set of activities to be monitored. A value for each activity of the set of activities is stored in a separate counter of a set of counters, forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. The set of activities are grouped into subsets. The stored values corresponding to each activity in each subset are summed, forming a total value for each subset. The total value of each subset is multiplied by a factor corresponding to the subset, forming a scaled value for each subset. The scaled value of each subset is summed, forming a power usage value. A power manager adjusts the operational parameters of the unit based on a comparison of the power usage value to a threshold value.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Michael Stephen Floyd
  • Patent number: 8261276
    Abstract: A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: September 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Richard James Eickemeyer, Susan Elizabeth Eisen, Michael Stephen Floyd, Hans Mikael Jacobson, Jeffrey R. Summers
  • Publication number: 20120216210
    Abstract: Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.
    Type: Application
    Filed: April 30, 2012
    Publication date: August 23, 2012
    Inventors: William Joseph Armstrong, Michael Stephen Floyd, Ronald Nick Kalla, Larry Scott Leitner, Balaram Sinharoy
  • Patent number: 8209698
    Abstract: Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: June 26, 2012
    Assignee: International Business Machines Corporation
    Inventors: William Joseph Armstrong, Michael Stephen Floyd, Ronald Nick Kalla, Larry Scott Leitner, Balaram Sinharoy
  • Patent number: 8156287
    Abstract: A data processing system includes a processor, a unit that includes a multi-level cache, a prefetch system and a memory. The data processing system can operate in a first mode and a second mode. The prefetch system can change behavior in response to a desired power consumption policy set by an external agent or automatically via hardware based on on-chip power/performance thresholds.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: April 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Miles Robert Dooley, Michael Stephen Floyd, David Scott Ray, Bruce Joseph Ronchetti
  • Patent number: 8145797
    Abstract: A processor supporting thread-execution-state-sensitive supervisory commands provides a mechanism for executing supervisory commands for live threads. The commands may be sent from a service processor or another primary processor in the system or may be supplied by the processor itself through supervisory software control. Since the state of execution of one or more threads may change dynamically within a processor core, an external processor will not know the thread execution state at the time the command operates. The method and apparatus provide a command set and logic that supports selective execution of particular commands directed at “alive” threads (or threads in some other determinable execution state), whereby the command is performed only on resources and/or execution units depending on the actual state of thread execution when the command operates within the processor.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: March 27, 2012
    Assignee: International Business Machines Corporation
    Inventor: Michael Stephen Floyd
  • Patent number: 8055477
    Abstract: A benchmark tester retrieves a voltage margin that corresponds to a device that a system includes. The voltage margin indicates an additional amount of voltage to apply to a nominal voltage that, when added, results in the device operating at a power limit while executing a worst-case power workload. Next, the benchmark tester (or thermal power management device) sets an input voltage for the device to a value equal to the sum of the voltage margin and the nominal voltage. The benchmark tester then dynamically benchmark tests the system, which includes adjusting the device's frequency and input voltage while ensuring that the device does not exceed the device's power limit. In turn, the benchmark tester records a guaranteed minimum performance boost for the system based upon a result of the benchmark testing.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Harold W. Chase, Soraya Ghiasi, Michael Stephen Floyd, Joshua David Friedrich, Steven Paul Hartman, Norman Karl James, Malcolm Scott Ware, Richard L. Willaman
  • Patent number: 8001394
    Abstract: A computer-implemented method and a system for managing power in a multi-core microprocessor are provided. A power management control microarchitecture in a chiplet translates a first command comprising a power setting. A chiplet comprises a processor core and associated memory cache. The power management control microarchitecture comprises power mode registers, power mode adjusters, translators, and microarchitectural power management techniques. The power management control microarchitecture sets microarchitectural power management techniques according to the power setting. The global power management controller issues the first command. The global power management controller may reside either on or off of the microprocessor.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: August 16, 2011
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Michael Stephen Floyd
  • Patent number: 7996703
    Abstract: Exemplary embodiments provide a computer-implemented method and a system for a startup cycle for a cycle deterministic start. An initializing mechanism applies power to a microprocessor. The initializing mechanism initializes the configuration of the microprocessor. The initializing mechanism initializes a timer. The initializing mechanism then sends a clock start command to the microprocessor. The clocks on the microprocessor are started. Upon the clocks starting, the timer begins and allows temporary transients, such as voltage droop due to a large instantaneous change in demand for current due to the commencement of clock switching. Responsive to the timer reaching a target value, an interrupt unit sends a system reset interrupt. Responsive to the interrupt unit sending the system reset interrupt, an instruction fetch unit fetches a first instruction. This operation will be deterministic to the state of the rest of the microprocessor memory elements (latches, arrays, et al.).
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: August 9, 2011
    Assignee: International Business Machines Corporation
    Inventors: Michael Stephen Floyd, Norman Karl James, Jeffrey William Kellington, Larry S. Leitner
  • Patent number: 7979750
    Abstract: A method, apparatus, and computer program product are disclosed in a data processing system for synchronizing the triggering of multiple hardware trace facilities using an existing bus. The multiple hardware trace facilities include a first hardware trace facility and a second hardware trace facility. The data processing system includes a first processor that includes the first hardware trace facility and first processing units that are coupled together utilizing the system bus, and a second processor that includes the second hardware trace facility and second processing units that are coupled together utilizing the system bus. Information is transmitted among the first and second processing units utilizing the system bus when the processors are in a normal, non-tracing mode, where the information is formatted according to a standard system bus protocol.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ra'ed Mohammad Al-Omari, Michael Stephen Floyd, Paul Frank Lecocq
  • Patent number: 7962887
    Abstract: Sensors on the integrated circuit are used to detect the current operating state of the chip, such as frequency, voltage, temperature characteristics, or variation in the integrated circuit manufacturing process. In response, the integrated circuit may choose to modify operational parameters (such as frequency, voltage, or power-down states) in order to dynamically and autonomously maintain an optimal performance and/or power-efficiency operational point.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Carl John Anderson, Michael Stephen Floyd, Norman Karl James, Phillip John Restle
  • Publication number: 20100268975
    Abstract: A method for estimating power consumption within a multi-core microprocessor chip is provided. An authorized user selects a set of activities to be monitored. A value for each activity of the set of activities is stored in a separate counter of a set of counters, forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. The set of activities are grouped into subsets. The stored values corresponding to each activity in each subset are summed, forming a total value for each subset. The total value of each subset is multiplied by a factor corresponding to the subset, forming a scaled value for each subset. The scaled value of each subset is summed, forming a power usage value. A power manager adjusts the operational parameters of the unit based on a comparison of the power usage value to a threshold value.
    Type: Application
    Filed: April 15, 2009
    Publication date: October 21, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Michael Stephen Floyd