Abstract: The subject technology provides for removing a source of delay in a phase-locked loop (PLL) by causing the output rising edge to occur at the same time as the input rising edge. The subject technology replicates the amount of delay experienced along an input reference signal path to the PLL as close as possible using a same circuit configuration and bias circuits as in the input reference signal path. For example, a timing alignment circuit containing a replica circuit adds compensation delay to a negative feedback loop signal to match the feedback loop delay with the reference path delay. The delay of the reference signal path is estimated and added into the replica circuit. The delay characteristics of these two paths negate one another such that the phases of the input reference signal and the feedback loop signal become phase-locked at the input to the PLL.

Abstract: The subject technology provides for removing a source of delay in a phase-locked loop (PLL) by causing the output rising edge to occur at the same time as the input rising edge. The subject technology replicates the amount of delay experienced along an input reference signal path to the PLL as close as possible using a same circuit configuration and bias circuits as in the input reference signal path. For example, a timing alignment circuit containing a replica circuit adds compensation delay to a negative feedback loop signal to match the feedback loop delay with the reference path delay. The delay of the reference signal path is estimated and added into the replica circuit. The delay characteristics of these two paths negate one another such that the phases of the input reference signal and the feedback loop signal become phase-locked at the input to the PLL.

Abstract: A fully automated pharmaceutical product packaging machine is capable of selectively depositing one or more different solid pharmaceutical products into an individual cavity for each of a plurality of individual patient product package cavities. The system employs a plurality of solid pharmaceutical product dispensing canisters which are capable of selectively dispensing a pre-designated number of solid pharmaceutical products. The machine fills a template containing temporary storage cavities and the template is automatically positioned over a sheet of clear plastic material containing a plurality of cavities corresponding to the cavities in the template. A barrier between the cavities in the template and the sheet of clear plastic material is moved and the pharmaceuticals in the template cavities drop into the corresponding cavities in the clear plastic sheet of material.

Abstract: A pressure relief vent includes an enclosure and at least one blocking element. The enclosure defines an air flow channel through a thickness of the enclosure. The enclosure includes at least one guide member that defines a track oriented transverse to a depth axis through the thickness. The at least one blocking element is held within track and is translatable between a seated position and a displaced position. The at least one blocking element plugs the air flow channel when in the seated position, and the air flow channel is at least partially unobstructed when the at least one blocking element is in the displaced position. The at least one blocking element is configured to be moved from the seated position to the displaced position by positive air pressure on an interior side of the enclosure to permit outbound air flow through the air flow channel.

Abstract: A method for inspecting a marine vessel underdeck utilizes a video camera such as a digital video camera with a magnifying or telephoto lens. The method produces a magnified image on a monitor for viewing by an inspector that appears to be no more than about 24 inches (61 cm) away. The method includes the step of filming the underdeck of a distance of about 40-70 feet (12-21 m). The lens provides a focal length of between about 15 feet (4.6 m) and 150 feet (46 m). Thus the method is conducted at a workable focal range of between about 15 feet (4.6 m) and 150 feet (46 m). The lens preferably has a focal length of between 30 feet (9 m) and 75 feet (23m). The method includes the step of scanning the suspect area of the underdeck of a speed of about 1 inch (2.54 cm) per second to three feet (91.4 cm) per second. The preferred method contemplates scanning of the suspect area of a rate of between about 0.5-1 foot (15.2-30.5 cm) per second.

Abstract: A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ).

Abstract: A method for inspecting a marine vessel underdeck utilizes a video camera such as a digital video camera with a magnifying or telephoto lens. The method produces a magnified image on a monitor for viewing by an inspector that appears to be no more than about 24 inches (61 cm) away. The method includes the step of filming the uuderdeck of a distance of about 40-70 feet (12-21 m). The lens provides a focal length of between about 15 feet (4.6 m) and 150 feet (46 m). Thus the method is conducted at a workable focal range of between about 15 feet (4.6 m) and 150 feet (46 m). The lens preferably has a focal length of between 30 feet (9 m) and 75 feet (23 m). The method includes the step of scanning the suspect area of the underdeck of a speed of about 1 inch (2.54 cm) per second to three feet (91.4 cm) per second. The preferred method contemplates scanning of the suspect area of a rate of between about 0.5-1 foot (15.2-30.5 cm) per second.

Abstract: A clock frequency division circuit receives delay value, synchronization signal, and external clock signal of a given frequency. The clock division circuit includes (a) a decode circuit receiving delay value and providing set of initial count values; (b) one or more counters each receiving input clock signal derived from the external clock signal and providing frequency divided output signal having a frequency a fraction of the given frequency, and each receiving a corresponding one of the initial count values, and wherein, subsequent to detecting a transition in the synchronization signal, each counter provides transition in the frequency divided output signal after a time period represented by corresponding initial count value; and (c) synchronization circuit that is reset by the synchronization signal, the synchronization circuit providing a gating signal enabling output of the frequency divided output signal after expiration of initial count value. The one or more counters may be cascaded.

Abstract: A clock frequency division circuit receives delay value, synchronization signal, and external clock signal of a given frequency. The clock division circuit includes (a) a decode circuit receiving delay value and providing set of initial count values; (b) one or more counters each receiving input clock signal derived from the external clock signal and providing frequency divided output signal having a frequency a fraction of the given frequency, and each receiving a corresponding one of the initial count values, and wherein, subsequent to detecting a transition in the synchronization signal, each counter provides transition in the frequency divided output signal after a time period represented by corresponding initial count value; and (c) synchronization circuit that is reset by the synchronization signal, the synchronization circuit providing a gating signal enabling output of the frequency divided output signal after expiration of initial count value. The one or more counters may be cascaded.

Abstract: A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ).

Abstract: A fully automated pharmaceutical product packaging machine is capable of selectively depositing one or more different solid pharmaceutical products into an individual cavity for each of a plurality of individual patient product package cavities. The system employs a plurality of solid pharmaceutical product dispensing canisters which are capable of selectively dispensing a pre-designated number of solid pharmaceutical products. The machine fills a template containing temporary storage cavities and the template is automatically positioned over a sheet of clear plastic material containing a plurality of cavities corresponding to the cavities in the template. A barrier between the cavities in the template and the sheet of clear plastic material is moved and the pharmaceuticals in the template cavities drop into the corresponding cavities in the clear plastic sheet of material.

Abstract: A method for detecting capacitor variation in a device comprises operating an oscillator in the device, the oscillator being an Inductive-Capacitive (LC) oscillator and including an inductor of known value and a capacitor under test, comparing an output of the oscillator to a reference output, and evaluating variation for a plurality of capacitors in the device based on the comparing.

Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.

Abstract: A method for inspecting a marine vessel underdeck utilizes a video camera such as a digital video camera with a magnifying or telephoto lens. The method produces a magnified image on a monitor for viewing by an inspector that appears to be no more than about 24 inches (61 cm) away. The method includes the step of filming the underdeck of a distance of about 40-70 feet (12-21 m). The lens provides a focal length of between about 15 feet (4.6 m) and 150 feet (46 m). Thus the method is conducted at a workable focal range of between about 15 feet (4.6 m) and 150 feet (46 m). The lens preferably has a focal length of between 30 feet (9 m) and 75 feet (23 m). The method includes the step of scanning the suspect area of the underdeck of a speed of about 1 inch (2.54 cm) per second to three feet (91.4 cm) per second. The preferred method contemplates scanning of the suspect area of a rate of between about 0.5-1 foot (15.2-30.5 cm) per second.

Abstract: When dynamically varying a number of active paths in a system, a desired return loss is maintained. Certain embodiments enable dynamic varying of the impedance of parallel signal paths in a system responsive to the number of active ones of the parallel paths dynamically changing, in order to maintain a relatively constant impedance match between a source and the combination of parallel paths, thereby retaining a desired return loss.

Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.

Abstract: High conversion rates are achieved in an analog to digital converter by tailoring the substrate type to specific operational elements of the converter. Embodiments place sample and hold processing circuitry on a substrate type having properties that allow for faster processing at high sampling/clock frequencies. Other operational elements of the converter are constructed on at least one other substrate type in keeping with the remainder of the circuitry for which the converter is being implemented. The sample and hold substrate may be implemented on any material which is capable of faster processing, such as silicon germanium, gallium arsenide, silicon bipolar, BiCMOS, and the like. Other portions may be implemented on a more CMOS substrate. Such systems and methods are able to implement analog-to digital conversion for broadband signals at high speeds without the need for extensive timing compensation, while also avoiding problems due to noise from further digital processing circuitry.

Abstract: When dynamically varying a number of active paths in a system, a desired return loss is maintained. Certain embodiments enable dynamic varying of the impedance of parallel signal paths in a system responsive to the number of active ones of the parallel paths dynamically changing, in order to maintain a relatively constant impedance match between a source and the combination of parallel paths, thereby retaining a desired return loss.

Abstract: Systems and methods which implement degeneration circuitry in a single-ended amplifier circuit to mitigate distortion associated with one or more amplifier components are disclosed. A degeneration circuit of embodiments adds an impedance to cancel the second-order distortion of an amplifier transistor of a single-ended amplifier circuit. A bias circuit may be provided to minimize bias offset between an amplifier transistor and a corresponding degeneration transistor.

Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.