Abstract: A method for data transmission in a hierarchically organized data transmission network wherein a central arithmetic unit cyclicly enables local concentrators to transmit data which the concentrators receive from a number of terminals undertakes a check at every concentrator by means of a change detector to determine whether incoming data has changed in comparison to a preceeding inquiry. When a change has occurred, all relative data are immediately transmitted to the arithmetic unit, otherwise, a short acknowledge character is transmitted. A time-redundant inquiry/acknowledge procedure is thus avoided.

Abstract: A method for the bidirectional data exchange between integrated building blocks through a multiprocessor bus in time multiplex operation determined by a pulse frame synchronizing signal fed to the building blocks includes:(a) fixing a monitor channel for bus access control information and fixing a data channel within the pulse frame;(b) checking the monitor channel with a building block desiring bus access for possibly available control information;(c) setting control information of the building block if the multi-processor bus is free; and(d) transmitting the data in the data channel.

Abstract: A monolithically integratable transmission system for binary information has at least one address source which is connected to at least one address sink via an address bus. The address sink is respectively allocated to a register means connected to a data bus. A clock generator generates a first clock signal and a non-overlapping, phase-shifted second clock signal. The address bus and the data bus are precharged during the first clock signal and access of an addressed register means to the data bus occurs during the second clock signal. In the time span between the two clock signals, the address bus is charged with the address signals by discharging.

Abstract: Method for monitored transfer of control signals at interfaces of digital systems wherein a request signal is transferred by a first system via a request line to a second system, information concerning the cause of the request signal is taken by the second system from a status register of the first system, and the status register is subsequently reset, which comprises providing the first system with both a first and a second status register; storing the information concerning the cause of the request signal in the first status register which has outputs connected to respective inputs of the second status register; connecting the second status register to the second system when a read signal delivered by the second system is present; severing the connection between the first and the second status registers during the presence of the read signal and a subsequent clock cycle of the first system; monitoring by the second system of a readout of the second status register; and resetting respective cells of the firs