Abstract: An integrated circuit is described herein that includes a semiconductor substrate. First and second piezoresistive sensors are on or in the substrate where each have a respective sensing axis extending in first and second directions respectively parallel with a surface of the substrate, where the second direction is perpendicular to the first direction. A third piezoresistive sensor is on or in the substrate and has a respective sensing axis extending in a third direction parallel with the surface of the substrate and neither parallel nor perpendicular to the first and second directions.

Abstract: An integrated circuit comprises a semiconductor substrate having a surface. A lateral resistor is arranged in a first plane parallel to the surface of the substrate. A vertical reference resistor comprises a layer arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. This layer is doped to promote current flow in the second plane. The vertical reference resistor further comprises a first trench and a second trench coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and the second planes and are doped to impede current flow in the vertical direction. A cross-section of the first and second trenches is two-fold rotationally symmetric around the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.

Abstract: An electronic device includes an ADC, a multiplexer, a voltage reference circuit, an analog circuit, and a digital circuit. The ADC has a signal input, a reference input, and an output. The multiplexer has signal inputs and a signal output coupled to the signal input of the ADC. The voltage reference circuit has an output coupled to the reference input of the ADC, a first strain sensor coupled to a first signal input of the multiplexer, a second strain sensor coupled to a second signal input of the multiplexer, and a temperature sensor. The analog circuit has an input coupled to a battery, and an output coupled to a fourth signal input of the multiplexer. The digital circuit is coupled to the output of the ADC and stores correction parameters for correcting a converted battery voltage value from the ADC.

Abstract: A force sensor including a semiconductor die, and a die pad coupled to the semiconductor die, the semiconductor die configured to detect a force in the die pad. In addition, the force sensor includes a mold compound covering the semiconductor die and having an outer perimeter, a first side, and a second side opposite the first side, the outer perimeter extending between the first side and the second side, the die pad exposed out of the mold compound along the first side. Further, the force sensor includes a mounting frame engaged with the die pad along the second side of the mold compound, the mounting frame including multiple mounting pads extended outward in multiple directions from the outer perimeter.

Abstract: An example semiconductor package includes a semiconductor die configured to detect a force. In addition, the semiconductor package includes a mold compound covering the semiconductor die. Further, the semiconductor package includes an engagement surface including a pattern of projections adapted to engage with a mounting surface on a member of interest.

Abstract: An electronic device includes an ADC, a multiplexer, a voltage reference circuit, an analog circuit, and a digital circuit. The ADC has a signal input, a reference input, and an output. The multiplexer has signal inputs and a signal output coupled to the signal input of the ADC. The voltage reference circuit has an output coupled to the reference input of the ADC, a first strain sensor coupled to a first signal input of the multiplexer, a second strain sensor coupled to a second signal input of the multiplexer, and a temperature sensor. The analog circuit has an input coupled to a battery, and an output coupled to a fourth signal input of the multiplexer. The digital circuit is coupled to the output of the ADC and stores correction parameters for correcting a converted battery voltage value from the ADC.

Abstract: An integrated circuit comprises a semiconductor substrate having a surface. A lateral resistor is arranged in a first plane parallel to the surface of the substrate. A vertical reference resistor comprises a layer arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. This layer is doped to promote current flow in the second plane. The vertical reference resistor further comprises a first trench and a second trench coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and the second planes and are doped to impede current flow in the vertical direction. A cross-section of the first and second trenches is two-fold rotationally symmetric around the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.

Abstract: An integrated circuit comprises a semiconductor substrate having a surface. A lateral resistor is arranged in a first plane parallel to the surface of the substrate. A vertical reference resistor comprises a layer arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. This layer is doped to promote current flow in the second plane. The vertical reference resistor further comprises a first trench and a second trench coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and the second planes and are doped to impede current flow in the vertical direction. A cross-section of the first and second trenches is two-fold rotationally symmetric around the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.

Abstract: In described examples, a circuit includes an analog frontend arranged to generate an analog stress compensating signal in response to a to-be-compensated analog signal and a first-axis stress sensing signal. The analog frontend can comprise a first precision component (e.g., 220) arranged on a piezoelectric material and arranged to generate the to-be-compensated analog signal that is affected by a stress exerted in the piezoelectric material and a directional stress sensor arranged on the piezoelectric material and coupled to the first precision component. The directional stress sensor is arranged to generate the first-axis sensing signal in response to a longitudinal resultant of a stress exerted in the piezoelectric material. A compensating circuit is arranged to generate a compensated output signal in response to the compensating analog signal and to-be-compensated analog signal.

Abstract: An integrated circuit is described herein that includes a semiconductor substrate. First and second piezoresistive sensors are on or in the substrate where each have a respective sensing axis extending in first and second directions respectively parallel with a surface of the substrate, where the second direction is perpendicular to the first direction. A third piezoresistive sensor is on or in the substrate and has a respective sensing axis extending in a third direction parallel with the surface of the substrate and neither parallel nor perpendicular to the first and second directions.

Abstract: An integrated circuit comprises a semiconductor substrate having a surface. A lateral resistor is arranged in a first plane parallel to the surface of the substrate. A vertical reference resistor comprises a layer arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. This layer is doped to promote current flow in the second plane. The vertical reference resistor further comprises a first trench and a second trench coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and the second planes and are doped to impede current flow in the vertical direction. A cross-section of the first and second trenches is two-fold rotationally symmetric around the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.

Abstract: A chassis assembly and method for including a component carrier in an electronic device. The assembly may include a carrier for housing a component for integration into the system. The carrier includes a frame constructed to at least partially contain the electronic portions of the component. A handle is pivotally coupled to the frame. The handle may rotate between an engaging orientation and a securing orientation. A pinion portion is included on the handle. The pinion portion may engage with a corresponding rack formed in the chassis to control movement of the carrier with respect to the chassis. A securing mechanism is disposed on an end of the handle opposite the pinion portion. The securing mechanism may be implemented to secure the handle in a securing orientation wherein the end of the handle, generally opposite the pinion portion, is disposed adjacent the frame. A securing mechanism such as a latch may be included to prevent rotation of the handle with respect to the frame.

Abstract: An optical disk cassette has a disk eject mechanism that ejects a disk such as a DVD or CD. The disk eject mechanism has pushrod, transfer and kick out portions. The pushrod portion slides relative to a side of the cassette case. Pivotally mounted within the case, the kick out portion pushes a disk to eject it from the case. The transfer portion translates pushrod motion to motion of the kick out portion. In a preferred embodiment, the disk eject mechanism is a unitary body, with pushrod, transfer and kick out portions made homogeneously as a single entity, the pushrod portion being a resilient joining elbow. In another preferred embodiment, the disk eject mechanism has a transfer portion that is a rack and a pinion. The rack extends from the pushrod portion and the pinion is attached to or formed as part of the kick out portion.

Abstract: An optical disk mechanism has a housing with at least one disk entry/exit aperture. A disk guide, such as a plate, is aligned with and guides an optical disk through the disk entry/exit aperture. Two beams rotatably support at least one roller and a drive mechanism. Flexing and biasing the roller towards the disk, the two beams maintain a rotational axis of the roller parallel to the disk and accommodate varying separation between the roller and the disk guide. The two beams are closely spaced and non-coplanar, and may be part of a double-beam mount. The double-beam mount attaches the two beams to the housing and to a frame, which positions the roller near the disk guide and the disk entry/exit aperture. Sliding the disk along the plate or other disk guide, the roller is reversible to drive the disk in or out through the disk entry/exit aperture.

Abstract: An optical disk cassette has a cassette case with a disk retention device. A free end of the disk retention device acts upon an edge of the optical disk, opposably displacing during insertion and ejection of the optical disk. The device and disk are at equilibrium when the free end is displaced by the full diameter of the disk. When the disk is displaced in the insertion or ejection direction, the free end urges the disk in the insertion or ejection direction, assisting with the optical disk insertion or ejection respectively. Embodiments may have the disk retention device including one or more retainers. Each retainer may have a free end and opposing fixed end, and be flexible or have a flexible region. The free end slides along or otherwise contacts the circumferential edge of the optical disk, exerting a force upon it during optical disk insertion, retention and ejection.

Abstract: An optical disk mechanism has a housing with at least one disk entry/exit aperture. A disk guide, such as a plate, is aligned with and guides an optical disk through the disk entry/exit aperture. Two beams rotatably support at least one roller and a drive mechanism. Flexing and biasing the roller towards the disk, the two beams maintain a rotational axis of the roller parallel to the disk and accommodate varying separation between the roller and the disk guide. The two beams are closely spaced and non-coplanar, and may be part of a double-beam mount. The double-beam mount attaches the two beams to the housing and to a frame, which positions the roller near the disk guide and the disk entry/exit aperture. Sliding the disk along the plate or other disk guide, the roller is reversible to drive the disk in or out through the disk entry/exit aperture.

Abstract: An optical disk cassette has a disk eject mechanism that ejects a disk such as a DVD or CD. The disk eject mechanism has pushrod, transfer and kick out portions. The pushrod portion slides relative to a side of the cassette case. Pivotally mounted within the case, the kick out portion pushes a disk to eject it from the case. The transfer portion translates pushrod motion to motion of the kick out portion. In a preferred embodiment, the disk eject mechanism is a unitary body, with pushrod, transfer and kick out portions made homogeneously as a single entity, the pushrod portion being a resilient joining elbow. In another preferred embodiment, the disk eject mechanism has a transfer portion that is a rack and a pinion. The rack extends from the pushrod portion and the pinion is attached to or formed as part of the kick out portion.

Abstract: A chassis assembly for an electronic device such as a storage device. The assembly includes a chassis for housing various functional components included in the electronic device. A sub-housing for containing a waste heat generating device, a device which requires temperature moderation, is included. The sub-housing defines a first airflow exhaust path for exhausting air in a first direction and a second airflow exhaust path for exhausting air in a second direction. The directing of airflow from the sub-housing is based on a chassis enclosure configuration such as to allow for the implementation of a common component including a component enclosure in a variety of chassis form factors.

Abstract: A chassis assembly and method for including a component carrier in an electronic device. The assembly may include a carrier for housing a component for integration into the system. The carrier includes a frame constructed to at least partially contain the electronic portions of the component. A handle is pivotally coupled to the frame. The handle may rotate between an engaging orientation and a securing orientation. A pinion portion is included on the handle. The pinion portion may engage with a corresponding rack formed in the chassis to control movement of the carrier with respect to the chassis. A securing mechanism is disposed on an end of the handle opposite the pinion portion. The securing mechanism may be implemented to secure the handle in a securing orientation wherein the end of the handle, generally opposite the pinion portion, is disposed adjacent the frame. A securing mechanism such as a latch may be included to prevent rotation of the handle with respect to the frame.