Abstract: A sequence of control voltage levels are applied to a control signal line capacitively coupled to a floating diffusion node of a pixel to sequentially adjust a voltage level of the floating diffusion node. A pixel output signal representative of the voltage level of the floating diffusion node is compared with a reference voltage to identify a first control voltage level of the sequence of control voltage levels for which the voltage level of the floating diffusion node exceeds the reference voltage.

Abstract: A sequence of control voltage levels are applied to a control signal line capacitively coupled to a floating diffusion node of a pixel to sequentially adjust a voltage level of the floating diffusion node. A pixel output signal representative of the voltage level of the floating diffusion node is compared with a reference voltage to identify a first control voltage level of the sequence of control voltage levels for which the voltage level of the floating diffusion node exceeds the reference voltage.

Abstract: A sequence of control voltage levels are applied to a control signal line capacitively coupled to a floating diffusion node of a pixel to sequentially adjust a voltage level of the floating diffusion node. A pixel output signal representative of the voltage level of the floating diffusion node is compared with a reference voltage to identify a first control voltage level of the sequence of control voltage levels for which the voltage level of the floating diffusion node exceeds the reference voltage.

Abstract: Photocharge is integrated within a first plurality of pixels of an integrated-circuit image sensor during a first exposure interval. A read-out signal is output from each pixel of the first plurality of pixels upon conclusion of the first exposure interval, each read-out signal indicating a respective level of photocharge integrated within the corresponding pixel during the first exposure interval. Photocharge is also integrated within a second plurality of pixels during a second exposure interval that transpires concurrently with the first exposure interval and has a duration not more than half the duration of the first exposure interval. A read-out signal is output from each pixel of the second plurality of pixels at least twice with respect to the second exposure interval, with each such read-out signal indicating a respective level of photocharge integrated within the corresponding pixel during at least a portion of the second exposure interval.

Abstract: A sequence of control voltage levels are applied to a control signal line capacitively coupled to a floating diffusion node of a pixel to sequentially adjust a voltage level of the floating diffusion node. A pixel output signal representative of the voltage level of the floating diffusion node is compared with a reference voltage to identify a first control voltage level of the sequence of control voltage levels for which the voltage level of the floating diffusion node exceeds the reference voltage.

Abstract: An integrated-circuit image sensor generates, as constituent reference voltages of a first voltage ramp, a first sequence of linearly related reference voltages followed by a second sequence of exponentially related reference voltages. The integrated-circuit image sensor compares the constituent reference voltages of the first voltage ramp with a first signal level representative of photocharge integrated within a pixel of the image sensor to identify a first reference voltage of the constituent reference voltages that is exceeded by the first signal level.

Abstract: An integrated-circuit image sensor generates, as constituent reference voltages of a first voltage ramp, a first sequence of linearly related reference voltages followed by a second sequence of exponentially related reference voltages.

Abstract: The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine whether memory references from different processor cores are interfering with each other as the memory references are processed by a memory system. If memory references from different processor cores are interfering with each other, the system time-multiplexes the processing of memory references between processor cores, so that a block of consecutive memory references from a given processor core is processed by the memory system before memory references from other processor cores are processed.

Abstract: The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine whether memory references from different processor cores are interfering with each other as the memory references are processed by a memory system. If memory references from different processor cores are interfering with each other, the system time-multiplexes the processing of memory references between processor cores, so that a block of consecutive memory references from a given processor core is processed by the memory system before memory references from other processor cores are processed.

Abstract: Disclosed herein are circuits in which a plurality of clock signals are generated by corresponding clock generators from one or more common clock references. The clock generators accept control values that specify the phases of the individual clocks. The actual phase of each clock signal potentially varies during operation, and the phases of the various clock signal are generally independent of each other. To detect or measure phase relationships, the disclosed circuits evaluate or compare the control values using arithmetic logic.

Abstract: Disclosed herein are circuits in which a plurality of clock signals are generated by corresponding clock generators from one or more common clock references. The clock generators accept control values that specify the phases of the individual clocks. The actual phase of each clock signal potentially varies during operation, and the phases of the various clock signal are generally independent of each other. To detect or measure phase relationships, the disclosed circuits evaluate or compare the control values using arithmetic logic.