Patents by Inventor Michael T. Clark

Michael T. Clark has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10612340
    Abstract: A wellbore plug isolation system and method for positioning plugs to isolate fracture zones in a horizontal, vertical, or deviated wellbore is disclosed. The system/method includes a wellbore casing laterally drilled into a hydrocarbon formation, a wellbore setting tool (WST) that sets a large inner diameter (ID) restriction sleeve member (RSM), and a restriction plug element (RPE). The WST is positioned along with the RSM at a desired wellbore location. After the WST sets and seals the RSM, a conforming seating surface (CSS) is formed in the RSM. The CSS is shaped to engage/receive RPE deployed into the wellbore casing. The engaged/seated RPE isolates heel ward and toe ward fluid communication of the RSM to create a fracture zone. The RPE's are removed or left behind prior to initiating well production without the need for a milling procedure. A large ID RSM diminishes flow constriction during oil production.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: April 7, 2020
    Assignee: GEODYNAMICS, INC.
    Inventors: Philip Martin Snider, Kevin R. George, John T. Hardesty, Michael D. Wroblicky, Nathan G. Clark, James A. Rollins, David S. Wesson
  • Patent number: 10480276
    Abstract: A wellbore plug isolation system and method for positioning plugs to isolate fracture zones in a horizontal, vertical, or deviated wellbore is disclosed. The system/method includes a wellbore casing laterally drilled into a hydrocarbon formation, a wellbore setting tool (WST) that sets a large inner diameter (ID) restriction sleeve member (RSM), and a restriction plug element (RPE). The WST is positioned along with the RSM at a desired wellbore location. After the WST sets and seals the RSM, a conforming seating surface (CSS) is formed in the RSM. The CSS is shaped to engage/receive RPE deployed into the wellbore casing. The engaged/seated RPE isolates heel ward and toe ward fluid communication of the RSM to create a fracture zone. The RPE's are removed or left behind prior to initiating well production without the need for a milling procedure. A large ID RSM diminishes flow constriction during oil production.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: November 19, 2019
    Assignee: GEODYNAMICS, INC.
    Inventors: Philip Martin Snider, Kevin R. George, John T. Hardesty, Michael D. Wroblicky, Nathan G. Clark, James A. Rollins, David S. Wesson
  • Publication number: 20190298441
    Abstract: An electrophysiology catheter is disclosed having a balloon with a membrane. Electrodes may be disposed on the membrane. Each electrode may include a radiopaque marker. The markers may have different forms, e.g., alphanumeric or polygonal, to facilitate visualization of the electrodes using a bi-stable image and allow for selection of the appropriate electrodes to be energized during ablation of tissue. The inventive subject matter allows for proper orientation of electrodes on the balloon under a two-dimensional imaging system. This allows the operator or physician to determine if certain electrodes are adjacent or contiguous to the posterior surface of the left atrium and ablate such posterior surface for shorter duration or at a lower power to create an effective transmural lesion on the posterior wall of the left atrium while reducing the chances of damaging the adjacent anatomical structures.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Inventors: Jeffrey L. CLARK, Michael D. BANANDO, Christopher T. BEECKLER, Darius D. EGHBAL, Kevin J. HERRERA, Joseph T. KEYES, Christopher BIRCHARD
  • Publication number: 20190303230
    Abstract: Systems, apparatuses, and methods for implementing a hardware enforcement mechanism to enable platform-specific firmware visibility into an error state ahead of the operating system are disclosed. A system includes at least one or more processor cores, control logic, a plurality of registers, platform-specific firmware, and an operating system (OS). The control logic allows the platform-specific firmware to decide if and when the error state is visible to the OS. In some cases, the platform-specific firmware blocks the OS from accessing the error state. In other cases, the platform-specific firmware allows the OS to access the error state such as when the OS needs to unmap a page. The control logic enables the platform-specific firmware, rather than the OS, to make decisions about the replacement of faulty components in the system.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Inventors: Dean A. Liberty, Vilas K. Sridharan, Michael T. Clark, Jelena Ilic, David S. Christie, James R. Williamson, Cristian Constantinescu
  • Patent number: 10223162
    Abstract: Systems, apparatuses, and methods for tracking system resource utilization of guest virtual machines (VMs). Counters may be maintained to track resource utilization of different system resources by different guest VMs executing on the system. When a guest VM initiates execution, stored values may be loaded into the resource utilization counters. While the guest VM executes, the counters may track the resource utilization of the guest VM. When the guest VM terminates execution, the counter values may be written to a virtual machine control block (VMCB) corresponding to the guest VM. Scaling factors may be applied to the counter values to normalize the values prior to writing the values to the VMCB. A cloud computing environment may utilize the tracking mechanisms to guarantee resource utilization levels in accordance with users' service level agreements.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: March 5, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael T. Clark, Jay Fleischman, Thaddeus S. Fortenberry, Maurice B. Steinman
  • Publication number: 20180181496
    Abstract: Methods, devices, and systems for determining an address in a physical memory which corresponds to a virtual address using a skewed-associative translation lookaside buffer (TLB) are described. A virtual address and a configuration indication are received using receiver circuitry. A physical address corresponding to the virtual address is output if a TLB hit occurs. A first subset of a plurality of ways of the TLB is configured to hold a first page size. The first subset includes a number of the ways based on the configuration indication. A physical address corresponding to the virtual address is retrieved from a page table if a TLB miss occurs, and at least a portion of the physical address is installed in a least recently used way of a subset of a plurality of ways the TLB, determined according to a replacement policy based on the configuration indication.
    Type: Application
    Filed: December 23, 2016
    Publication date: June 28, 2018
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John M. King, Michael T. Clark
  • Publication number: 20170031719
    Abstract: Systems, apparatuses, and methods for tracking system resource utilization of guest virtual machines (VMs). Counters may be maintained to track resource utilization of different system resources by different guest VMs executing on the system. When a guest VM initiates execution, stored values may be loaded into the resource utilization counters. While the guest VM executes, the counters may track the resource utilization of the guest VM. When the guest VM terminates execution, the counter values may be written to a virtual machine control block (VMCB) corresponding to the guest VM. Scaling factors may be applied to the counter values to normalize the values prior to writing the values to the VMCB. A cloud computing environment may utilize the tracking mechanisms to guarantee resource utilization levels in accordance with users' service level agreements.
    Type: Application
    Filed: April 13, 2016
    Publication date: February 2, 2017
    Inventors: Michael T. Clark, Jay Fleischman, Thaddeus S. Fortenberry, Maurice B. Steinman
  • Patent number: 7937574
    Abstract: In an embodiment, a microcode unit for a processor is contemplated. The microcode unit comprises a microcode memory storing a plurality of microcode routines executable by the processor, wherein each microcode routine comprises two or more microcode operations. Coupled to the microcode memory, the sequence control unit is configured to control reading microcode operations from the microcode memory to be issued for execution by the processor. The sequence control unit is configured to stall issuance of microcode operations forming a body of a loop in a first routine of the plurality of microcode routines until a loop counter value that indicates a number of iterations of the loop is received by the sequence control unit.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: May 3, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael T. Clark, Jelena Ilic, Syed Faisal Ahmed, Michael T. DiBrino
  • Patent number: 7831816
    Abstract: A processor receives a command via a sideband interface on the processor to read processor state information, e.g., CPUID information. The sideband interface provides the command information to a microcode engine in the processor that executes the command to retrieve the designated processor state information at an appropriate instruction boundary and retrieves the processor state information. That processor information is stored in local buffers in the sideband interface to avoid modifying processor state. After the microcode engine completes retrieval of the information and the sideband interface command is complete, execution returns to the normal flow in the processor. Thus, the processor state information may be obtained non-destructively during processor runtime.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: November 9, 2010
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wallace P. Montgomery, David F. Tobias, Michael T. Clark
  • Patent number: 7761672
    Abstract: A system and method for copying and initializing a block of memory. To copy several data entities from a source region of memory to a destination region of memory, an instruction may copy each data entity one at a time. If an aggregate condition is determined to be satisfied, multiple data entities may be copied simultaneously. The aggregate condition may rely on an aggregate data size, the size of the data entities to be copied, and the alignment of the source and destination addresses.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: July 20, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael T. Clark, Matthew Rafacz
  • Patent number: 7665002
    Abstract: A single test access port, such as a JTAG-based debug port may be utilized to perform debug operations on logic cores of a multi-core integrated circuit, such as a multi-core processor. The shared debug port may respond to a particular command to enter a debugging mode and may be configured to forward all commands and data to a debugging controller of the integrated circuit during debugging. A mask register may be used to indicate which logic cores of the multi-core integrated circuit should be debugged. Additionally, custom debugging commands may include mask or core select fields to indicate which logic cores should be affected by the particular command. Debugging mode may be initialized for one or more logic cores either externally, such as be asserted a DBREQ signal, or internally, such as by configuring one or more breakpoints.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: February 16, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Scott A. White, Michael T. Clark, Timothy J. Wood
  • Publication number: 20090300332
    Abstract: A processor receives a command via a sideband interface on the processor to read processor state information, e.g., CPUID information. The sideband interface provides the command information to a microcode engine in the processor that executes the command to retrieve the designated processor state information at an appropriate instruction boundary and retrieves the processor state information. That processor information is stored in local buffers in the sideband interface to avoid modifying processor state. After the microcode engine completes retrieval of the information and the sideband interface command is complete, execution returns to the normal flow in the processor. Thus, the processor state information may be obtained non-destructively during processor runtime.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 3, 2009
    Inventors: Wallace P. Montgomery, David F. Tobias, Michael T. Clark
  • Publication number: 20090187777
    Abstract: A processing node that is integrated onto a single integrated circuit chip includes a first processor core and a second processor core. The processing node also includes an operating system executing on either of the first processor core and the second processor core. The operating system may monitor a current utilization of the first processor core and the second processor core. The operating system may cause the first processor core to operate at performance level that is lower than a system maximum performance level and the second processor core to operate at performance level that is higher than the system maximum performance level in response to detecting the first processor core operating below a utilization threshold.
    Type: Application
    Filed: January 22, 2009
    Publication date: July 23, 2009
    Inventor: Michael T. Clark
  • Publication number: 20090177866
    Abstract: A method of operating a computer system. A first processor sends a first unit of binary information to an input/output (I/O) unit. The I/O unit then conveys the first unit of binary information to a functional unit in the computer system. A system response from the functional unit is then received by the I/O unit, which forwards the system response to the first processor. The system response is also stored in a first buffer. After a predetermined delay time has elapsed, the system response is then forwarded to the second processor.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 9, 2009
    Inventors: Michael L. Choate, Mark D. Nicol, Michael T. Clark, Scott A. White, Gregory A. Lewis, Todd Foster, Gerald D. Zuraski, JR.
  • Patent number: 7490254
    Abstract: A processing node that is integrated onto a single integrated circuit chip includes a first processor core and a second processor core. The processing node also includes an operating system executing on either of the first processor core and the second processor core. The operating system may monitor a current utilization of the first processor core and the second processor core. The operating system may cause the first processor core to operate at performance level that is lower than a system maximum performance level and the second processor core to operate at performance level that is higher than the system maximum performance level in response to detecting the first processor core operating below a utilization threshold.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: February 10, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Michael T. Clark
  • Publication number: 20090037932
    Abstract: A computer system includes a system memory, a plurality of processor cores, and an input/output (I/O) hub that may communicate with each of the processor cores. In response to detecting an occurrence of an internal system management interrupt (SMI), each of the processor cores may save to a system management mode (SMM) save state in the system memory, information corresponding to a source of the internal SMI. In response to detecting the internal SMI, each processor core may further initiate an I/O cycle to a predetermined port address within the I/O hub. The I/O hub may broadcast an SMI message to each of the processor cores in response to receiving the I/O cycle. Each of the processor cores may further save to the SMM save state in the system memory, respective internal SMI source information in response to receiving the broadcast SMI message.
    Type: Application
    Filed: August 1, 2007
    Publication date: February 5, 2009
    Inventors: Michael T. Clark, Jelena Ilic
  • Publication number: 20090024842
    Abstract: In an embodiment, a microcode unit for a processor is contemplated. The microcode unit comprises a microcode memory storing a plurality of microcode routines executable by the processor, wherein each microcode routine comprises two or more microcode operations. Coupled to the microcode memory, the sequence control unit is configured to control reading microcode operations from the microcode memory to be issued for execution by the processor. The sequence control unit is configured to stall issuance of microcode operations forming a body of a loop in a first routine of the plurality of microcode routines until a loop counter value that indicates a number of iterations of the loop is received by the sequence control unit.
    Type: Application
    Filed: July 17, 2007
    Publication date: January 22, 2009
    Inventors: Michael T. Clark, Jelena Ilic, Syed Faisal Ahmed, Michael T. DiBrino
  • Publication number: 20090006791
    Abstract: A system and method for copying and initializing a block of memory. To copy several data entities from a source region of memory to a destination region of memory, an instruction may copy each data entity one at a time. If an aggregate condition is determined to be satisfied, multiple data entities may be copied simultaneously. The aggregate condition may rely on an aggregate data size, the size of the data entities to be copied, and the alignment of the source and destination addresses.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventors: Michael T. Clark, Matthew Rafacz
  • Patent number: 7373484
    Abstract: A method of controlling write operations to a non-renamed register space includes receiving a write operation to a given register within the non-renamed register space. The method also includes determining whether a pending write operation to the given register exists. In response to determining that the pending write operation to the given register exists, the method includes blocking the write operation to the given register from being scheduled. However, in response to determining that the pending write operation to the given register does not exist, the method includes allowing the write operation to the given register to be scheduled. Further, if the pending write operation to the given register does not exist, the method includes allowing a subsequent write operation to a different register within the non-renamed register space to be scheduled.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: May 13, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Arun Radhakrishnan, Benjamin T. Sander, Michael A. Filippo, Michael T. Clark, David E. Kroesche
  • Patent number: D861746
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: October 1, 2019
    Assignee: Xerox Corporation
    Inventors: William T Clark, III, Michael F Leo, Stephen F Skrainar, Donald A Brown, David M Parsons