Abstract: The present disclosure relates to a pre-charge circuit including a first inverter which receives an early pre-charge signal and outputs an inverted early pre-charge signal, a first gate which receives a late pre-charge signal and a match line output signal and outputs an AND output signal, and a second gate which receives the inverted early pre-charge signal and the AND output signal and outputs an effective pre-charge signal.

Abstract: The present disclosure relates to a content addressable memory (CAM), and more particularly, to an algorithmic ternary content addressable memory (TCAM) that instantiates multiple copies of X-Y TCAMs. The structure includes a content addressable memory (CAM) and an array which instantiates multiple replicated copies of the CAM in a row direction and a column direction of the array.

Abstract: The present disclosure relates to a content addressable memory (CAM), and more particularly, to an algorithmic ternary content addressable memory (TCAM) that instantiates multiple copies of X-Y TCAMs. The structure includes a content addressable memory (CAM) and an array which instantiates multiple replicated copies of the CAM in a row direction and a column direction of the array.

Abstract: Words of data are maintained in content-addressable memory cells arranged in rows. Two of the rows are timing reference rows, and the remainder of the rows are data rows that maintain the words of data. The data rows form individual matchlines. A first of the reference rows forms a precharge reference matchline, and a second of the reference rows forms an evaluation reference matchline. The timing for the individual matchlines to precharge is based on the time to precharge the precharge reference matchline, and timing for the individual matchlines to evaluate a search word is based on the time for the evaluation reference matchline to evaluate the search word.

Abstract: Words of data are maintained in content-addressable memory cells arranged in rows. Two of the rows are timing reference rows, and the remainder of the rows are data rows that maintain the words of data. The data rows form individual matchlines. A first of the reference rows forms a precharge reference matchline, and a second of the reference rows forms an evaluation reference matchline. The timing for the individual matchlines to precharge is based on the time to precharge the precharge reference matchline, and timing for the individual matchlines to evaluate a search word is based on the time for the evaluation reference matchline to evaluate the search word.

Abstract: A ternary content addressable memory (TCAM) structure may activate individual groups of subarrays in the TCAM structure, during a non-search mode, at configurable intervals of time. The activating causes the TCAM structure to select locations and sequences in which subarrays of the TCAM structure are activated or deactivated. When activating, the TCAM structure is configured to perform a dummy search within the particular subarray. The activating reduces a change in current during transition between a search mode and the non-search mode.

Abstract: The present disclosure relates to content addressable memories (CAM), and more particularly, to a searchable CAM structure having self-reference matchline precharge and local feedback control and method of use. The present disclosure includes a structure which includes: a sense line connected to a sensing device; a feedback line connected to the sense line at a tap point between a first end and a second end of the sense line; and a local precharge controller connected to the tap point by the feedback line to control precharging of the sense line according to a state of the feedback line.

Abstract: A ternary content addressable memory (TCAM) structure may activate individual groups of subarrays in the TCAM structure, during a non-search mode, at configurable intervals of time. The activating causes the TCAM structure to select locations and sequences in which subarrays of the TCAM structure are activated or deactivated. When activating, the TCAM structure is configured to perform a dummy search within the particular subarray. The activating reduces a change in current during transition between a search mode and the non-search mode.

Abstract: Low leakage CAMs and method of searching low leakage CAMs. The method includes performing a pre-search and compare on a small number of pre-search bits with pre-search CAM cells powered to normal voltage levels at all times while the main-search CAM cells are powered to a lower voltage level. Only if a match is detected on the pre-search bits are the main-search CAM cells powered-up to normal voltage levels and the search of the main-search bits activated. The main-search CAM cells are powered to normal voltage levels during read and write operations.

Abstract: Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed.

Abstract: Low leakage CAMs and method of searching low leakage CAMs. The method includes performing a pre-search and compare on a small number of pre-search bits with pre-search CAM cells powered to normal voltage levels at all times while the main-search CAM cells are powered to a lower voltage level. Only if a match is detected on the pre-search bits are the main-search CAM cells powered-up to normal voltage levels and the search of the main-search bits activated. The main-search CAM cells are powered to normal voltage levels during read and write operations.

Abstract: Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed.

Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.

Abstract: An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; releasing the bit line from being held at a zero voltage potential when the memory cell is being accessed; charging the bit line to a first voltage potential greater in value than the zero voltage potential during an access of the memory cell, wherein charging the bit line to a first voltage potential occurs for a first predetermined period of time after access to the memory cell has begun; and sensing the memory cell contents during an access of the memory cell, wherein sensing of the memory cell contents occurs for a second predetermined period of time after access to the memory cell has begun.

Abstract: A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first voltage potential different than the zero voltage potential during an access of the memory cell; and sensing the memory cell contents when the associated bit line has reached the first voltage potential.

Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.

Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.

Abstract: A system for implementing row redundancy in integrated circuit memory devices includes one or more main subarrays having word line, bit line and memory cell devices, each of the one or more main subarrays including a set of support circuitry associated therewith. A discrete, redundant subarray is associated with the main subarrays, and also includes a set of support circuitry associated therewith. A common global bit line is shared by the main subarrays and the redundant subarray, and redundancy steering control circuitry is associated with the main subarrays and the redundant subarray. The redundancy steering control circuitry is configured such that word line activation of the main subarrays and the redundant subarray is performed in parallel with address compare operations performed by the redundancy steering control circuitry.

Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.

Abstract: A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.