Patents by Inventor Michael T. Klinglesmith
Michael T. Klinglesmith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230185747Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller’s performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: ApplicationFiled: February 8, 2023Publication date: June 15, 2023Inventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Patent number: 11604746Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: GrantFiled: July 22, 2020Date of Patent: March 14, 2023Assignee: SK hynix NAND Product Solutions Corp.Inventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Patent number: 11476168Abstract: Disclosed herein are structures and techniques for exposing circuitry in die testing. For example, in some embodiments, an integrated circuit (IC) die may include: first conductive contacts at a first face of the die; second conductive contacts at a second face of the die; die stack emulation circuitry; other circuitry; and a switch coupled to the second conductive contacts, the die stack emulation circuitry, and the other circuitry, wherein the switch is to couple the second conductive contacts to the other circuitry when the switch is in a first state, and the switch is to couple the die stack emulation circuitry to the other circuitry when the switch is in a second state different from the first state.Type: GrantFiled: April 9, 2018Date of Patent: October 18, 2022Assignee: Intel CorporationInventors: Terrence Huat Hin Tan, Rehan Sheikh, Michael T. Klinglesmith, Sukhbinder Takhar, Shi Hou Chong, Kok Hin Oon, Wai Loon Yip, Yudhishthira Kundu, Deepak R. Tanna
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Patent number: 11449446Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: GrantFiled: July 22, 2020Date of Patent: September 20, 2022Assignee: Intel CorporationInventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Patent number: 11144387Abstract: Embodiments include a serial bus controller that may be coupled to an in band serial peripheral interface (SPI) link, to request a write of data and a subsequent read of the data from a memory device and in response to the request to read the data, receive a bit error report and optionally correct the bit error over the in band SPI link. Embodiments include a memory device, e.g., a flash memory device, to detect and report the bit error over the in band SPI link, where the flash memory device, in response to a request to write and/or erase data, calculates or determines an error correction code (ECC) and stores corresponding parity data. In embodiments, after receiving a subsequent request to read the data, the flash memory device accesses the stored parity data to check the ECC for a bit error and if a bit error is detected, reports the detected bit error over the in band SPI link. Other embodiments may be described and claimed.Type: GrantFiled: April 29, 2019Date of Patent: October 12, 2021Assignee: INTEL CORPORATIONInventors: Zhenyu Zhu, William A. Stevens, Jr., Michael T. Klinglesmith, Mikal Hunsaker
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Publication number: 20200349100Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: ApplicationFiled: July 22, 2020Publication date: November 5, 2020Inventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Patent number: 10754808Abstract: Bridge logic is provided to receive a request from a device, where the request references an address of a secondary address space. The secondary address space corresponds to a subset of addresses in a configuration address space of a system, and the secondary address space corresponds to a first view of the configuration address space. The bridge logic uses a mapping table to translate the address into a corresponding address in the configuration address space, where addresses of the configuration address space correspond to a different second view of the configuration address space.Type: GrantFiled: December 20, 2015Date of Patent: August 25, 2020Assignee: Intel CorporationInventors: Prashant Sethi, Michael T. Klinglesmith, David J. Harriman, Reuven Rozic, Shanthanand Kutuva Rabindrananth
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Publication number: 20190311960Abstract: Disclosed herein are structures and techniques for exposing circuitry in die testing. For example, in some embodiments, an integrated circuit (IC) die may include: first conductive contacts at a first face of the die; second conductive contacts at a second face of the die; die stack emulation circuitry; other circuitry; and a switch coupled to the second conductive contacts, the die stack emulation circuitry, and the other circuitry, wherein the switch is to couple the second conductive contacts to the other circuitry when the switch is in a first state, and the switch is to couple the die stack emulation circuitry to the other circuitry when the switch is in a second state different from the first state.Type: ApplicationFiled: April 9, 2018Publication date: October 10, 2019Applicant: Intel CorporationInventors: Terrence Huat Hin Tan, Rehan Sheikh, Michael T. Klinglesmith, Sukhbinder Takhar, Shi Hou Chong, Kok Hin Oon, Wai Loon Yip, Yudhishthira Kundu, Deepak R. Tanna
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Publication number: 20190258539Abstract: Embodiments include a serial bus controller that may be coupled to an in band serial peripheral interface (SPI) link, to request a write of data and a subsequent read of the data from a slave device and in response to the request to read the data, receive a bit error report and optionally correct the bit error over the in band SPI link. Embodiments include a slave device, e.g., a flash memory device, to detect and report the bit error over the in band SPI link, where the flash memory device, in response to a request to write and/or erase data, calculates or determines an error correction code (ECC) and stores corresponding parity data. In embodiments, after receiving a subsequent request to read the data, the flash memory device accesses the stored parity data to check the ECC for a bit error and if a bit error is detected, reports the detected bit error over the in band SPI link. Other embodiments may be described and claimed.Type: ApplicationFiled: April 29, 2019Publication date: August 22, 2019Inventors: Zhenyu Zhu, William A. Stevens, JR., Michael T. Klinglesmith, Mikal Hunsaker
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Patent number: 10164880Abstract: In one embodiment, the present invention is directed to method for receiving a packet in a first agent, where the packet includes a first packet header with an expanded header indicator. Based on this indicator, the agent can determine if the packet includes one or more additional packet headers. If so, the agent can next determining if it supports information in the additional packet header based on a header identifier of the additional header. Other embodiments are described and claimed.Type: GrantFiled: November 14, 2014Date of Patent: December 25, 2018Assignee: Intel CorporationInventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Rohit R. Verma, Robert P. Adler
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Patent number: 10157160Abstract: In one embodiment, a method includes: receiving, via a sideband interface of a multi-root agent associated with a first root space and a second root space, a reset prepare signal to inform the multi-root agent that the first root space is to be reset; sending, via the sideband interface, an acknowledgement signal to acknowledge the reset prepare signal; receiving one or more transactions for the first root space from a fabric coupled to the multi-root agent; and terminating the one or more transactions responsive to the reset prepare signal, where the first root space is in a reset state when the one or more transactions are received. Other embodiments are described and claimed.Type: GrantFiled: September 25, 2015Date of Patent: December 18, 2018Assignee: Intel CorporationInventors: Michael T. Klinglesmith, Mikal C. Hunsaker, William Knolla, Hartej Singh
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Patent number: 10133670Abstract: In an example, a system-on-a-chip comprises a plurality of multi-core processors, such as four dual-core processors for eight total cores. Each of the processors connects to shared resources such as memory and peripherals via a shared uncore fabric. Because each input bus for each core can include hundreds of data lines, the number of lines into the shared uncore fabric can become prohibitive. Thus, inputs from each core are multiplexed, such as in a two-to-one configuration. The multiplexing may be a non-blocking, queued (such as FIFO) multiplexing to ensure that all packets from all cores are delivered to the uncore fabric. In certain embodiment, some smaller input lines may be provided to the uncore fabric non-multiplexed, and returns (outputs) from the uncore fabric to the cores may also be non-multiplexed.Type: GrantFiled: December 27, 2014Date of Patent: November 20, 2018Assignee: Intel CorporationInventors: Ramadass Nagarajan, Jose S. Niell, Michael T. Klinglesmith, Derek T. Bachand, Ganesh Kumar
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Patent number: 9990327Abstract: In one embodiment, a system includes: a first root space associated with a first root space identifier and including at least one first host processor and a first agent, the at least one first host processor and the first agent associated with the first root space identifier; a second root space associated with a second root space identifier and including at least one second host processor and a second agent, the at least one second host processor and the second agent associated with the second root space identifier; and a shared fabric to couple the first root space and the second root space, the shared fabric to route a transaction to the first root space or the second root space based at least in part on a root space field of the transaction. Other embodiments are described and claimed.Type: GrantFiled: October 12, 2015Date of Patent: June 5, 2018Assignee: Intel CorporationInventors: Michael T. Klinglesmith, Chang Yong Kang, Robert DeGruijl, Ioannis T. Schoinas, Darren Abramson, Khee Wooi Lee
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Publication number: 20180137074Abstract: Bridge logic is provided to receive a request from a device, where the request references an address of a secondary address space. The secondary address space corresponds to a subset of addresses in a configuration address space of a system, and the secondary address space corresponds to a first view of the configuration address space. The bridge logic uses a mapping table to translate the address into a corresponding address in the configuration address space, where addresses of the configuration address space correspond to a different second view of the configuration address space.Type: ApplicationFiled: December 20, 2015Publication date: May 17, 2018Applicant: Intel CorporationInventors: Prashant Sethi, Michael T. Klinglesmith, David J. Harrimann, Reuven Rozic
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Patent number: 9971711Abstract: Selected portions of an uncore fabric of a system-on-a-chip (SoC) or other embedded system are divided into two independent pipelines. Each pipeline operates independently of the other pipeline, and each accesses only one-half of the system memory, such as even or odd addresses in an interleaved memory. However, the two pipelines are tightly coupled to maintain coherency of the fabric. Coupling may be accomplished, for example, by a shared clock that is one-half of the base clock cycle for the fabric. Each incoming address may be processed by a deterministic hash, assigned to one of the pipelines, processed through memory, and then passed to a credit return.Type: GrantFiled: December 25, 2014Date of Patent: May 15, 2018Assignee: Intel CorporationInventors: Ramadass Nagarajan, Michael T. Klinglesmith, Joydeep Ray
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Patent number: 9753875Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.Type: GrantFiled: January 20, 2016Date of Patent: September 5, 2017Assignee: Intel CorporationInventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
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Patent number: 9658978Abstract: In one embodiment, a system-on-chip (SoC) can be configured to receive a request from a master agent in a fabric coupled to the master agent, send a show command grant to the master agent responsive to selection of the request by the fabric, receive a command portion of a transaction corresponding to the request in the fabric and determine a target agent to receive the transaction based on the command portion, and thereafter send a transaction grant to the master agent for the transaction. Other embodiments are described and claimed.Type: GrantFiled: March 13, 2014Date of Patent: May 23, 2017Assignee: Intel CorporationInventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari, Joseph Murray, Robert P. Adler
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Publication number: 20160357696Abstract: In one embodiment, a method includes: receiving, via a sideband interface of a multi-root agent associated with a first root space and a second root space, a reset prepare signal to inform the multi-root agent that the first root space is to be reset; sending, via the sideband interface, an acknowledgement signal to acknowledge the reset prepare signal; receiving one or more transactions for the first root space from a fabric coupled to the multi-root agent; and terminating the one or more transactions responsive to the reset prepare signal, where the first root space is in a reset state when the one or more transactions are received. Other embodiments are described and claimed.Type: ApplicationFiled: September 25, 2015Publication date: December 8, 2016Inventors: Michael T. Klinglesmith, Mikal C. Hunsaker, William Knolla, Hartej Singh
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Publication number: 20160357700Abstract: In one embodiment, a system includes: a first root space associated with a first root space identifier and including at least one first host processor and a first agent, the at least one first host processor and the first agent associated with the first root space identifier; a second root space associated with a second root space identifier and including at least one second host processor and a second agent, the at least one second host processor and the second agent associated with the second root space identifier; and a shared fabric to couple the first root space and the second root space, the shared fabric to route a transaction to the first root space or the second root space based at least in part on a root space field of the transaction. Other embodiments are described and claimed.Type: ApplicationFiled: October 12, 2015Publication date: December 8, 2016Inventors: Michael T. Klinglesmith, Chang Yong Kang, Robert DeGruijl, Ioannis T. Schoinas, Darren Abramson, Khee Wooi Lee
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Publication number: 20160335208Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: ApplicationFiled: July 29, 2016Publication date: November 17, 2016Inventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen