Abstract: A broadcast command packet protocol provides for significant reduction of the overhead associated with a data transfer operation and the consequent increase in throughput efficiency. IDENTIFY and SIMPLE TAG messages, along with a command descriptor block, are collapsed into a 24-byte packet which is broadcast to all target devices residing on a bus in a “burst” subsequent to an arbitration and a NULL SELECT phase. Multiple broadcast command packets are sequentially burst onto the data bus in back-to-back fashion, to one or more target devices subsequent to a single arbitration phase. Each target device verifies its own ID, queues up its intended commands, and subsequently arbitrates for control of the bus to executed the commands.

Abstract: An SCSI quick arbitration and select protocol reduces the timing overhead associated with multiple, sequential data transfer operations, thereby significantly increasing bus efficiencies and average throughput. The conventional arbitration and selection phases are collapsed into a quick arbitrated and select phase, whereby the current SCSI target hosts an arbitration proceeding without the bus transitioning to a bus free phase. The quick arbitrate and select phase is invoked by a current target device by broadcasting a QAS message code during the message-in phase of the current process. QAS capable devices snoop the bus, recognize the QAS message code and enter a quick arbitrate and select phase. A fairness algorithm grants control of the bus to a participating QAS target with the next lowest SCSI ID from that of the current QAS target.

Abstract: An integrated circuit provides for doubled data throughput by clocking data on both edges of an attached clock signal. The circuit includes an upper latch stack, responsive to the clock rising edge, and a lower latch stack responsive to the clock falling edge, each latch stack outputting a respective set and clear signal. An active overlap filter logically ORs the set and clear signals from the upper and lower latch stacks to a third set and clear signal which controls operation of an output latch. Data lines are connected to the upper and lower latch stacks, such that a first data signal is clocked to the circuit output during a clock rising edge transition and a second data signal is clocked to the output during a clock falling edge transition. Filter circuitry between the latch stacks and the output latch ensures that set and clear are not asserted simultaneously, thus providing for "glitch" free operation of the circuit.

Abstract: An automatic SCSI termination circuit has means detecting the occupied or vacant status of one or more SCSI interconnection ports and enables or disables termination, which is applied to the ports without need for manual intervention.