Patents by Inventor Michael T. Morse
Michael T. Morse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8829566Abstract: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor region proximate to a second type of semiconductor region. The first type of semiconductor is to absorb light in a first range of wavelengths and the second type of semiconductor to absorb light in a second range of wavelengths. A multiplication region is defined proximate to and separate from the absorption region. The multiplication region includes an intrinsic semiconductor region in which there is an electric field to multiply the electrons created in the absorption region.Type: GrantFiled: March 15, 2007Date of Patent: September 9, 2014Assignee: Intel CorporationInventors: Michael T. Morse, Olufemi I. Dosunmu, Ansheng Liu, Mario J. Paniccia
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Patent number: 8803268Abstract: A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.Type: GrantFiled: April 26, 2013Date of Patent: August 12, 2014Assignee: Intel CorporationInventors: John Heck, Ansheng Liu, Michael T. Morse, Haisheng Rong
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Publication number: 20130299932Abstract: A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.Type: ApplicationFiled: April 26, 2013Publication date: November 14, 2013Inventors: JOHN HECK, ANSHENG LIU, MICHAEL T. MORSE, HAISHENG RONG
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Patent number: 8435809Abstract: A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.Type: GrantFiled: September 25, 2009Date of Patent: May 7, 2013Assignee: Intel CorporationInventors: John Heck, Ansheng Liu, Michael T. Morse, Haisheng Rong
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Patent number: 8338857Abstract: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor region proximate to a second type of semiconductor region. The first type of semiconductor is to absorb light in a first range of wavelengths and the second type of semiconductor to absorb light in a second range of wavelengths. A multiplication region is defined proximate to and separate from the absorption region. The multiplication region includes an intrinsic semiconductor region in which there is an electric field to multiply the electrons created in the absorption region.Type: GrantFiled: August 28, 2010Date of Patent: December 25, 2012Assignee: Intel CorporationInventors: Michael T. Morse, Olufemi I. Dosunmu, Ansheng Liu, Mario J. Paniccia
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Patent number: 8278741Abstract: Sidewall photodetectors for integrated photonic devices and their method of manufacture. An embodiment includes a p-i-n film stack formed on a sidewall of a substrate semiconductor feature having sufficiently large area to accommodate the spot size of a multi-mode fiber. An embodiment includes a first sidewall photodetector coupled to a second sidewall photodetector by a waveguide, the first sidewall photodetector having an i-layer tuned to absorb a first wavelength of light incident to the first sidewall and pass a second wavelength of light to the second sidewall photodetector having an i-layer tuned to absorb the second wavelength.Type: GrantFiled: June 30, 2009Date of Patent: October 2, 2012Assignee: Intel CorporationInventors: Michael T. Morse, Mario J. Paniccia, Olufemi I. Dosunmu
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Publication number: 20110073972Abstract: A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.Type: ApplicationFiled: September 25, 2009Publication date: March 31, 2011Inventors: John Heck, Ansheng Liu, Michael T. Morse, Haisheng Rong
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Publication number: 20100327381Abstract: Sidewall photodetectors for integrated photonic devices and their method of manufacture. An embodiment includes a p-i-n film stack formed on a sidewall of a substrate semiconductor feature having sufficiently large area to accommodate the spot size of a multi-mode fiber. An embodiment includes a first sidewall photodetector coupled to a second sidewall photodetector by a waveguide, the first sidewall photodetector having an i-layer tuned to absorb a first wavelength of light incident to the first sidewall and pass a second wavelength of light to the second sidewall photodetector having an i-layer tuned to absorb the second wavelength.Type: ApplicationFiled: June 30, 2009Publication date: December 30, 2010Inventors: Michael T. Morse, Mario J. Paniccia, Olufemi I. Dosunmu
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Publication number: 20100320502Abstract: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor region proximate to a second type of semiconductor region. The first type of semiconductor is to absorb light in a first range of wavelengths and the second type of semiconductor to absorb light in a second range of wavelengths. A multiplication region is defined proximate to and separate from the absorption region. The multiplication region includes an intrinsic semiconductor region in which there is an electric field to multiply the electrons created in the absorption region.Type: ApplicationFiled: August 28, 2010Publication date: December 23, 2010Inventors: Michael T. Morse, Olufemi I. Dosunmu, Ansheng Liu, Mario J. Paniccia
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Patent number: 7741657Abstract: An avalanche photodetector is disclosed. An apparatus according to aspects of the present invention includes a semiconductor substrate layer including a first type of semiconductor material. The apparatus also includes a multiplication layer including the first type of semiconductor material disposed proximate to the semiconductor substrate layer. The apparatus also includes an absorption layer having a second type of semiconductor material disposed proximate to the multiplication layer such that the multiplication layer is disposed between the absorption layer and the semiconductor substrate layer. The absorption layer is optically coupled to receive and absorb an optical beam. The apparatus also includes an n+ doped region of the first type of semiconductor material defined at a surface of the multiplication layer opposite the absorption layer.Type: GrantFiled: July 17, 2006Date of Patent: June 22, 2010Assignee: Intel CorporationInventors: Alexandre Pauchard, Michael T. Morse
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Publication number: 20080012104Abstract: An avalanche photodetector is disclosed. An apparatus according to aspects of the present invention includes a semiconductor substrate layer including a first type of semiconductor material. The apparatus also includes a multiplication layer including the first type of semiconductor material disposed proximate to the semiconductor substrate layer. The apparatus also includes an absorption layer having a second type of semiconductor material disposed proximate to the multiplication layer such that the multiplication layer is disposed between the absorption layer and the semiconductor substrate layer. The absorption layer is optically coupled to receive and absorb an optical beam. The apparatus also includes an n+ doped region of the first type of semiconductor material defined at a surface of the multiplication layer opposite the absorption layer.Type: ApplicationFiled: July 17, 2006Publication date: January 17, 2008Inventors: Alexandre Pauchard, Michael T. Morse
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Patent number: 7233051Abstract: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor region proximate to a second type of semiconductor region. The first type of semiconductor is to absorb light in a first range of wavelengths and the second type of semiconductor to absorb light in a second range of wavelengths. A multiplication region is defined proximate to and separate from the absorption region. The multiplication region includes an intrinsic semiconductor region in which there is an electric field to multiply the electrons created in the absorption region.Type: GrantFiled: June 28, 2005Date of Patent: June 19, 2007Assignee: Intel CorporationInventors: Michael T. Morse, Olufemi I. Dosunmu, Ansheng Liu, Mario J. Paniccia
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Patent number: 7209623Abstract: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region defined along an optical waveguide. The absorption region includes a first type of semiconductor material having a first refractive index. The apparatus also includes a multiplication region defined along the optical waveguide. The multiplication region is proximate to and separate from the absorption region. The multiplication region includes a second type of semiconductor material having a second refractive index. The first refractive index greater than the second refractive index such that an optical beam directed through the optical waveguide is pulled towards the absorption region from the multiplication region and absorbed in the absorption region to create electron-hole pairs from the optical beam. The multiplication region includes first and second doped regions defined along the optical waveguide.Type: GrantFiled: May 3, 2005Date of Patent: April 24, 2007Assignee: Intel CorporationInventor: Michael T. Morse
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Patent number: 7088888Abstract: A waveguide Bragg grating (WBG) is apodized by varying the duty cycle of selected grating periods while fixing the pitch of the grating periods. In one embodiment, the WBG is implemented in a silicon substrate using polysilicon filled trenches of varying width while keeping the grating periods' pitch constant. The polysilicon trenches are formed so that if the width of one trench is increased compared to an adjacent grating period, the trench width in the other adjacent grating period (if present) is decreased.Type: GrantFiled: April 9, 2004Date of Patent: August 8, 2006Assignee: Intel CorporationInventors: Ansheng Liu, Shlomo Ovadia, Dean A. Samara-Rubio, Michael T. Morse
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Patent number: 7082248Abstract: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region defined along an optical waveguide. The absorption region includes a first type of semiconductor material having a first refractive index. The apparatus also includes a multiplication region defined along the optical waveguide. The multiplication region is proximate to and separate from the absorption region. The multiplication region includes a second type of semiconductor material having a second refractive index. The first refractive index greater than the second refractive index such that an optical beam directed through the optical waveguide is pulled towards the absorption region from the multiplication region and absorbed in the absorption region to create electron-hole pairs from the optical beam. The multiplication region includes first and second doped regions defined along the optical waveguide.Type: GrantFiled: October 4, 2005Date of Patent: July 25, 2006Assignee: Intel CorporationInventor: Michael T. Morse
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Patent number: 7043124Abstract: A method to form a taper in a semiconductor layer. In one embodiment, the semiconductor layer is formed on a cladding layer. A mask layer is formed on the semiconductor layer. The mask layer is patterned and etched to form at least an angled region and a thick region. An ion implantation process is performed so that the portion under the angled region is implanted to have an interface or surface that is angled relative to the surface of the cladding layer. This angled surface forms part of the vertical taper. The implanted region does not contact the cladding layer, leaving an unimplanted portion to serve as a waveguide. The portion under the thick region is not implanted, forming a coupling end of the taper.Type: GrantFiled: July 23, 2004Date of Patent: May 9, 2006Assignee: Intel CorporationInventors: Michael S. Salib, Michael T. Morse
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Patent number: 6989284Abstract: A method to form a taper in a semiconductor layer. In one embodiment, the semiconductor layer is formed on a cladding layer. A mask layer is formed on the semiconductor layer. The mask layer is patterned and etched to form at least an angled region and a thick region. An ion implantation process is performed so that the portion under the angled region is implanted to have an interface or surface that is angled relative to the surface of the cladding layer. This angled surface forms part of the vertical taper. The implanted region does not contact the cladding layer, leaving an unimplanted portion to serve as a waveguide. The portion under the thick region is not implanted, forming a coupling end of the taper.Type: GrantFiled: May 31, 2002Date of Patent: January 24, 2006Assignee: Intel CorporationInventors: Michael S. Salib, Michael T. Morse
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Patent number: 6987912Abstract: A method to form a semiconductor taper without etching the taper surfaces. In one embodiment, a semiconductor waveguide is formed on a workpiece having an unetched top surface; e.g., using a silicon insulator (SOI) wafer. A protective layer is formed on the waveguide. The protective layer is patterned and etched to form a mask that exposes a portion of the waveguide in the shape of the taper's footprint. In one embodiment, selective silicon epitaxy is used to grow the taper on the exposed portion of the waveguide so that the taper is formed without etched surfaces. Micro-loading effects can cause the upper surface of the taper to slope toward the termination end of the taper.Type: GrantFiled: March 23, 2004Date of Patent: January 17, 2006Assignee: Intel CorporationInventor: Michael T. Morse
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Patent number: 6956983Abstract: A method to form a semiconductor taper without etching the taper surfaces. In one embodiment, a semiconductor waveguide is formed on a workpiece having an unwatched top surface; e.g., using a silicone on insulator (SOI) wafer. A protective layer is formed on the waveguide. The protective layer is patterned and etched to form a mask that exposes a potion of the waveguide in the shape of the taper's footprint. In one embodiment, selective silicone epitaxy is used to grow the taper on the exposed portion of the waveguide so that the taper is formed without etched surfaces. Micro-loading effects can cause the upper surface of the taper to slope toward the termination end of the taper.Type: GrantFiled: May 31, 2002Date of Patent: October 18, 2005Assignee: Intel CorporationInventor: Michael T. Morse
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Patent number: 6950577Abstract: A waveguide Bragg grating (WBG) is apodized by varying the duty cycle of selected grating periods while fixing the pitch of the grating periods. In one embodiment, the WBG is implemented in a silicon substrate using polysilicon filled trenches of varying width while keeping the grating periods' pitch constant. The polysilicon trenches are formed so that if the width of one trench is increased compared to an adjacent grating period, the trench width in the other adjacent grating period (if present) is decreased.Type: GrantFiled: July 1, 2002Date of Patent: September 27, 2005Assignee: Intel CorporationInventors: Ansheng Liu, Shlomo Ovadia, Dean A. Samara-Rubio, Michael T. Morse