Abstract: An assembly including a boat and a cover. The cover covers and protects the boat. The boat is provided with one or more covered portion, and one or more uncovered portion. The cover includes a protective covering, and a boot. The protective covering defines a tolerance cut out adapted to receive a portion of the one or more uncovered portion when the protective covering is covering the object. The tolerance cut out has a length, a width and a perimeter. The boot is provided with an upstanding material flange, and a sealing system. The upstanding material flange extends about the perimeter of the tolerance cut out so as to define an opening aligned with the tolerance cut out, the upstanding material flange extends upwardly from the protective covering. The sealing system is positioned upstream of the tolerance cut out and on the upstanding material flange for sealing the upstanding material flange along the length of the tolerance cut out.

Abstract: A fuse link (50) is formed using a method which offers greater scalability of the general conductor system used to wire the device. An oxide mask (36) having the shape of a desired fuse link is formed over a thin metallization layer (34). A barrier layer (38) is formed over the thin metallization layer (34). A conductive layer (40) is formed over the barrier layer (38). A photoresist mask (42) supplied to the conductive layer (40), and the conductive layer is etched to formed interconnects (44, 46). Subsequently, the barrier layer (38) and thin metallization layer (34) are etched, thus rendering a fuse link (50) between interconnects (44, 46) under the oxide mask (36).

Abstract: A single layer polysilicon self-aligned transistor (52) is provided having a substantially vertical emitter contact region (62), such that the emitter contact region (62) does not require extending portions overlying the base region (60). Heavily doped silicided regions (68) are disposed adjacent the emitter (64) in a self-aligned process such that the base resistance of the device is minimized. A planar oxide layer (72) is formed such that the emitter contact region (62) are exposed without exposing other polysilicon gates of the integrated circuit. A metal layer (76) may be disposed over the planar oxide layer (72) to form a level of interconnects.

Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.

Abstract: A method of interconnecting metal layers in integrated circuits separated by an intermediate dielectric layer by forming first and pillar layers of metal, etching the pillar layer to form a pillar of electrically conducting material and etching the first level to form the first level lead. A layer of dielectric is applied to cover the pillar and first level lead. A layer of photoresist is deposited over the dielectric with a spin on technique to form a planar surface. The dielectric and photoresist are etched back with an equal etch rate until a top portion of the pillar is exposed. A second level lead is formed atop the pillar and planar top surface of the dielectric.

Abstract: A fuse link (50) is formed using a method which offers greater scalability of the general conductor system used to wire the device. An oxide mask (36) having the shape of a desired fuse link is formed over a thin metallization layer (34). A barrier layer (38) is formed over the thin metallization layer (34). A conductive layer (40) is formed over the barrier layer (38). A photoresist mask (42) supplied to the conductive layer (40), and the conductive layer is etched to formed interconnects (44, 46). Subsequently, the barrier layer (38) and thin metallization layer (34) are etched, thus rendering a fuse link (50) between interconnects (44, 46) under the oxide mask (36).

Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of the platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.

Abstract: A method for forming contact vias in order to make electrical connection between conductive interconnection layers is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.

Abstract: A method of processing an interlevel dielectric layer in a VLSI device having a plurality of leads which includes depositing a layer of photoresist over the dielectric layer. The photoresist is then patterned to open areas where interlevel contacts are to be formed and then heated to a sufficiently high temperature and for a sufficient time to remove solvents and obtain a desired slope surrounding the open areas. The photoresist and dielectric is etched to planarize the dielectric surface, to expose the underlying leads and to remove all of the photoresist.