Abstract: A first vendor generates one or more files corresponding to an integrated circuit having one or more registers. A content of the files is structured for at least one of: (i) incorporation into a boot code sequence; or (ii) access by the boot code sequence during execution. The boot code sequence is configured to initialize the registers responsive to the content during execution. The first vendor transmits the files to at least one of: (i) a second vendor that develops the boot code sequence; or (ii) a manufacturer of a system that includes the integrated circuit and the boot code sequence. A computer accessible medium comprises instructions which, when executed, generate the files described above and/or comprises the files. A method may include receiving, from the first vendor, the files described above. The content of the files is incorporated into the boot code sequence.

Abstract: A non-volatile memory system is presented having a boot code section, wherein the size of the boot code section may be programmably selected. One embodiment of the non-volatile memory system includes a memory array, a logic unit, a control unit, and a program store. The memory array includes multiple non-volatile memory cells (e.g., flash EEPROM cells). The memory array is divided into memory blocks of equal size. A number of the memory blocks are allocated for boot code storage, forming a boot code section of the memory array. The control unit controls storage of data within and retrieval of data from the memory array. The control unit includes a configuration register having a boot code section size field. The contents of the boot code section size field determine the number of memory blocks making up the boot code section. The logic unit is coupled between the control unit and the memory array, and receives address, data, and control signals from an external source.

Abstract: A non-volatile memory system is presented having a boot code section, wherein the size of the boot code section may be programmably selected. One embodiment of the non-volatile memory system includes a memory array, a logic unit, a control unit, and a program store. The memory array includes multiple non-volatile memory cells (e.g., flash EEPROM cells). The memory array is divided into memory blocks of equal size. A number of the memory blocks are allocated for boot code storage, forming a boot code section of the memory array. The control unit controls storage of data within and retrieval of data from the memory array. The control unit includes a configuration register having a boot code section size field. The contents of the boot code section size field determine the number of memory blocks making up the boot code section. The logic unit is coupled between the control unit and the memory array, and receives address, data, and control signals from an external source.

Abstract: A hardware-based system for configuring a CPU and chip set logic of a computer system to allow data transfers on both the rising and falling edges of a bus clock signal. The CPU and chip set logic each include bus communication circuitry for transferring data, a storage unit, and a configuration circuit. The contents of the storage unit determine whether the respective bus communication circuitry transfers data on only one or on both clock edges. Initially, the bus communication circuits transfer data on only one clock edge. The configuration circuits of the CPU and chip set logic are connected by a single signal line and participate in a serial exchange of signals over the single signal line. The configuration circuits modify the contents of the respective storage units dependent upon an outcome of the serial exchange of signals. The configuration circuit of the CPU initiates the exchange of signals, transmitting a query signal.

Abstract: A power management unit is provided that includes a plurality of configuration registers for storing configuration information to set various operational parameters of the power management unit. A program register is mapped within the configuration space of the computer system and is utilized to store a value which sets the I/O address of the index register. The program register is written during the initialization of the power management unit, and may be associated with a predetermined default value. Once the program register has been set with a value indicating the I/O address of the index register, accesses to the configuration registers are achieved by first writing an offset value to the index register. Subsequently, configuration data may be written into or read out of a designated configuration register by executing an appropriate cycle to the address of the configuration data register, which may be mapped one word location beyond that of the index register.

Abstract: A shared interface to a non-volatile memory including a first storage area for BIOS and a second storage area (e.g., for multimedia data) provides an integrated configuration which saves the cost and space of duplicating memory elements to support multiple data and program types in personal computers. The BIOS information is shadowed from the non-volatile memory to a second memory (e.g., a PC main memory). Thereafter, the BIOS information is accessed in the second memory and the information of the second storage area is accessed via the shared interface. The storage may be integrated upon personal computer system boards without a degradation in performance or an increase in pin count of the board memory because the same pins are used at different times for different memory portions. Accordingly, a storage system is provided to meet the demands of increasing storage requirements without a corresponding increase in cost, space or performance.

Abstract: A method for testing the functioning of a non-cacheable region within a cache having a cache controller programmed with a write-back write policy and a non-cacheable region included in an image memory region corresponding to a physical memory region. A first data pattern is written to the cache tagged at a first addressable location of a cacheable region in the physical memory region. A second data pattern is written to the cache tagged at a second addressable location in the image memory region contained within both the non-cacheable region and the cacheable region and corresponding to the first addressable location. The data stored in the cache and tagged at the first addressable location and corresponding to the non-cacheable region only of the second addressable location is read to determine whether the first data pattern remains in the cache thereby indicating that the non-cacheable region is functioning correctly.

Abstract: A system and method for providing a microprocessor with a software accessible serial number. A plurality of programmable fuses on the processor are encoded with a value representative of a serial number. Circuitry is provided on the processor for transferring the value encoded on the programmable fuses to a machine specific or general purpose register or storage device. The machine specific or general purpose register or storage unit is software accessible.

Abstract: A method and apparatus for providing a microprocessor serial number. A small, nonvolatile random access memory is packaged with the CPU die to provide a storage space for a CPU serial number which can be programmed before leaving the factory. Both the CPU die and the nonvolatile RAM die reside within the cavity of the package. Connection between the two die is provided by conventional wire bonding.

Abstract: A multiprocessing system comprising a plurality of processors and a plurality of I/O devices. A central interrupt control unit functionally intercouples the plurality of processors and I/O devices. The central interrupt control unit is configured to receive interrupt signals from the I/O devices and is configured to distribute interrupt signals to the processors. One of the processors is configured as a master test processor to control a test mode for testing the central interrupt control unit. The master test processor is further configured to release the other processors and emulate a multiprocessing environment.

Abstract: A system is described for facilitating operation of a peripheral bus, such as a PCI bus, at a higher clock frequency. Each of the devices resident on the PCI bus include certain configuration registers, including MIN.sub.-- GNT and MAX.sub.-- LAT, which provide configuration parameters to various system resources. In addition, each of the devices resident on the PCI bus include a status register with a dedicated 66 MHzCAPABLE bit. The dedicated status bit indicates whether the PCI device is capable of operating in a 66 MHz environment. As a result, each device can be polled during system initialization to determine if all of the PCI devices will support 66 MHz operation. If the system determines that the clock frequency will change due to a change in the system configuration (such as PCI devices being added or removed from the PCI bus), the configuration registers of each of the PCI devices can be modified to insure proper operation at the new clock frequency.

Abstract: A system and method for providing information regarding system support capabilities to a processor. A computer system includes a processing unit, a main memory and a first plurality of peripherals coupled to a first bus. A bus bridge couples the first bus to a second bus and a second plurality of support peripherals are coupled to the second bus. The processing unit is capable of providing requests for system support information to the bus bridge and the first and second plurality support peripherals. The peripherals are configured to provide responses to the request. The processing unit stores the responses and uses the information received to enable and disable its functional units or the peripheral's functional units accordingly. In one embodiment, the requests and information are provided along a dedicated serial interface. In another, the requests and information are provided as specialized bus cycles along the CPU bus.

Abstract: A processing system comprising at least one processing unit, a plurality of I/O devices, and a central interrupt control unit intercoupling the processing unit and the plurality of I/O devices. The central interrupt control unit is configured to receive interrupt signals from the I/O devices and is configured to distribute said interrupt signals to the processing unit. The central interrupt control unit is further configured to provide a signal simulative of an interrupt signal to simplify the testing process.

Abstract: A method and apparatus for software to access a microprocessor serial number. Provision of the serial number allows the manufacturer better control over its product and also permits software vendors to register their products. The serial number is encrypted using a pair of encryption keys to prevent unauthorized changes. At least one of the encryption keys is itself encoded to prevent unauthorized access, while permitting software to access the serial number.

Abstract: A method and apparatus for providing, maintaining and upgrading the software lock of a microprocessor. When a processor upgrade occurs, software that was serialized to the previously installed processor detects that it is running on an unauthorized processor. The software initiates a reauthorization process based on a reauthorization use profile. The temporary re-enabling of the software is allowed if the authorization service is not available.

Abstract: A method and apparatus for encrypting and decrypting a microprocessor serial number. First and second encryption keys and a serial number are provided in microprocessor machine specific registers. The serial number is encrypted using the first key. The encrypted serial number is encrypted using the second key. The first encryption key may be encrypted along with the serial number using the second key. The double encrypted serial number is then stored in memory provided for that purpose.

Abstract: The present invention permits a primary launch engine to display the names of, and information relating to, and cause the execution of diagnostic/test programs and/or batch-type routines for the silicon validation of microprocessors not only in existence at the time the primary launch engine is developed and compiled, but also, diagnostic/test programs and/or batch-type routines for the silicon validation of microprocessors that are developed and/or modified after the primary launch engine is developed and compiled without requiring modifications to, or the recompilation of, the primary launch engine. To do so, the present invention utilizes specialized data files consisting of one or more screen definition files and/or one or more script files wherein each screen definition file contains necessary menu structure and response information for each of the available diagnostic/test programs and wherein each of the script files contains sequencing and parameter information for each of the batch-type routines.

Abstract: A system is described for facilitating operation of a peripheral bus, such as a PCI bus, at different clock frequencies. One embodiment includes an enable line (66 MHzENABLE) connected to each of the devices resident on the PCI bus. The enable line is passively pulled high through a pull-up resistor if all devices resident on the PCI bus can support high frequency operation (such as, for example, 66 MHz). If any device cannot support high frequency operation, the device internally connects the enable line to ground in accordance with present industry specifications. Thus, the enable line will be passively high only if all of the PCI devices support high frequency operation, but will be asserted low if any device cannot support high frequency operation. The invention also includes a dedicated status bit to permit the system to warn the operator of discrepancies between device and bus capabilities.

Abstract: A power management unit that includes a software writable enable register for receiving an SMI enable bit when the generation of an immediate SMI is desired. When the enable bit is set, an SMI flag register causes the assertion of an SMI signal. The power management unit further includes a reason register that is also writable via software command. The reason register is written prior to the setup of the enable bit with a "reason value" indicative of the reason a pending SMI is being requested. The immediate system management interrupt source allows initiating software to indicate the reason it is requesting an SMI, and causes an associated SMI to be asserted with minimal latency. The immediate system management interrupt source further allows the system management interrupt service routine to quickly determine the reason for the immediate SMI, thereby allowing simplified and more efficient SMI service routines and further allowing greater flexibility in programming.

Abstract: A computer system is provided including a processor and a parallel port configured to transfer data to or from a peripheral device. The parallel port includes a data buffer for receiving data transferred on a system bus when the processor executes a write cycle to the parallel port. A control unit associated with the parallel port decodes the address signals of the system bus to selectively latch data within the data buffer, and generates handshake signals to the peripheral device to indicate that write data is presently contained within the data buffer. The peripheral device consequently receives the data and provides an acknowledge signal to the control unit. The control unit thereafter generates a ready signal to indicate to the processor that the data has been written into the peripheral device.