Patents by Inventor Michael Tak-Kei Ching
Michael Tak-Kei Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7352234Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).Type: GrantFiled: January 22, 2007Date of Patent: April 1, 2008Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., Nancy David Dillon, legal representative, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin, John B. Dillon
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Patent number: 7288973Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.Type: GrantFiled: September 27, 2005Date of Patent: October 30, 2007Assignee: Rambus Inc.Inventors: Jared LeVan Zerbe, Michael Tak-kei Ching, Abhijit M. Abhyankar, Richard M. Barth, Andy Peng-Pui Chan, Paul G. Davis, William F. Stonecypher
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Patent number: 7167039Abstract: A method of operating an integrated circuit including an output driver. The method includes storing a value in a register, wherein the value is representative of a voltage swing setting of an output driver. The voltage swing setting of the output driver is adjusted using a counter that holds a count value representing an update to the voltage swing setting. The count value is updated in accordance with a signal that indicates an adjustment to the voltage swing setting. In addition, an integrated circuit memory device comprising an output driver, a register and a counter is provided. The counter updates a count value in response to a signal that indicates a direction to adjust the count value.Type: GrantFiled: July 14, 2004Date of Patent: January 23, 2007Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., Nancy David Dillon, legal representative, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin, John B. Dillon, deceased
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Patent number: 7091761Abstract: An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current 5 river receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.Type: GrantFiled: June 8, 2005Date of Patent: August 15, 2006Assignee: Rambus, Inc.Inventors: Donald C. Stark, Jun Kim, Kurt T. Knorpp, Michael Tak-Kei Ching, Natsuki Kushiyama
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Patent number: 6975160Abstract: A system including an integrated circuit memory device. The integrated circuit device comprises a register to store a value representative of an output voltage setting. A circuit holds a value representative of an adjustment to the output voltage setting. An output driver outputs a drive voltage during a calibration operation, wherein a signal is generated based on a comparison between a signal derived from the drive voltage and a reference voltage. The signal updates the value representative of the adjustment to the output voltage setting.Type: GrantFiled: December 14, 2004Date of Patent: December 13, 2005Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., Nancy David Dillon, legal representative, Michael Tak-Kei Ching, William E. Stonecynher, Andy Peng-Pui Chan, Matthew M. Griffin, John B. Dillon, deceased
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Patent number: 6975159Abstract: A method of operating a memory system that includes an integrated circuit memory device is provided. A value representing an output voltage setting of an output driver of the memory device is stored in a register. The output driver outputs the drive voltage. A signal derived from the drive voltage is compared to a reference signal to generate a signal that indicates an adjustment to the output voltage setting. The output voltage setting of the output driver is adjusted using a counter that holds a count value representing an update to the output voltage setting. The count value is updated in accordance with a signal that indicates the adjustment to the output voltage setting.Type: GrantFiled: November 5, 2004Date of Patent: December 13, 2005Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., Nancy David Dillon, legal representative, Michael Tak-Kei Ching, William F. Stonecynher, Andy Peng-Pui Chan, Matthew M. Griffin, John B. Dillon, deceased
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Patent number: 6949958Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.Type: GrantFiled: October 28, 2002Date of Patent: September 27, 2005Assignee: Rambus Inc.Inventors: Jared LeVan Zerbe, Michael Tak-kei Ching, Abhijit M. Abhyankar, Richard M. Barth, Andy Peng-Pui Chan, Paul G. Davis, William F. Stonecypher
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Patent number: 6922092Abstract: An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.Type: GrantFiled: December 8, 2003Date of Patent: July 26, 2005Assignee: Rambus Inc.Inventors: Donald C. Stark, Jun Kim, Kurt T. Knorpp, Michael Tak-Kei Ching, Natsuki Kushiyama
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Patent number: 6870419Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).Type: GrantFiled: July 23, 2003Date of Patent: March 22, 2005Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., Nancy David Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin, John B. Dillon
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Publication number: 20040119511Abstract: An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.Type: ApplicationFiled: December 8, 2003Publication date: June 24, 2004Applicant: Rambus Inc.Inventors: Donald C. Stark, Jun Kim, Kurt T. Knorpp, Michael Tak-Kei Ching, Natsuki Kushiyama
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Patent number: 6661268Abstract: An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.Type: GrantFiled: December 11, 2001Date of Patent: December 9, 2003Assignee: Rambus Inc.Inventors: Donald C. Stark, Jun Kim, Kurt T. Knorpp, Michael Tak-Kei Ching, Natsuki Kushiyama
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Patent number: 6608507Abstract: A memory system and method of adjusting an output driver characteristic of a memory device that is included in the memory system. The method includes providing a command to the memory device that specifies a calibration mode and, during the calibration mode, driving a voltage level onto the first signal line using a first output driver. A first voltage level is derived from an amount of voltage swing generated by the first output driver driving the voltage level onto the first signal line. The method also includes: actively coupling a first comparator to the first signal line; when the first comparator is coupled to the first signal line, comparing the first voltage level with a reference voltage using the first comparator; and adjusting the amount of voltage swing to arrive at a calibrated voltage swing level. In addition, the method includes actively isolation the first comparator from the first signal line upon exiting the calibration mode.Type: GrantFiled: August 29, 2002Date of Patent: August 19, 2003Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., John B. Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin
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Patent number: 6556052Abstract: A semiconductor controller device to control the operation of a semiconductor memory device. The controller device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. In addition, the controller device includes a voltage divider, coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. In addition, the controller device also includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.Type: GrantFiled: September 12, 2001Date of Patent: April 29, 2003Inventors: Billy Wayne Garrett, Jr., John B. Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin
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Publication number: 20030053489Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.Type: ApplicationFiled: October 28, 2002Publication date: March 20, 2003Applicant: Rambus, Inc.Inventors: Jared LeVan Zerbe, Michael Tak-Kei Ching, Abhijit M. Abhyankar, Richard M. Barth, Andy Peng-Pui Chan, Paul G. Davis, William F. Stonecypher
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Publication number: 20020196059Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).Type: ApplicationFiled: August 29, 2002Publication date: December 26, 2002Inventors: Billy Wayne Garrett, John B. Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin, Nancy David Dillon
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Patent number: 6473439Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.Type: GrantFiled: October 9, 1998Date of Patent: October 29, 2002Assignee: Rambus IncorporatedInventors: Jared LeVan Zerbe, Michael Tak-kei Ching, Abhijit M. Abhyankar, Richard M. Barth, Andy Peng-Pui Chan, Paul G. Davis, William F. Stonecypher
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Patent number: 6462591Abstract: A semiconductor memory device including an array of memory cells. The memory device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. The memory device further includes a voltage divider coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. The memory device further includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.Type: GrantFiled: June 14, 2001Date of Patent: October 8, 2002Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., John B. Dillon, by Nancy David Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin
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Publication number: 20020070771Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).Type: ApplicationFiled: September 12, 2001Publication date: June 13, 2002Inventors: Billy Wayne Garrett, John B. Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin, Nancy David Dillon
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Publication number: 20020043997Abstract: An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.Type: ApplicationFiled: December 11, 2001Publication date: April 18, 2002Applicant: Rambus Inc.Inventors: Donald C. Stark, Jun Kim, Kurt T. Knorpp, Michael Tak-Kei Ching, Natsuki Kushiyama
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Publication number: 20020017929Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).Type: ApplicationFiled: June 14, 2001Publication date: February 14, 2002Inventors: Billy Wayne Garrett, John B. Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin, Nancy David Dillon