Patents by Inventor Michael Teener

Michael Teener has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050251601
    Abstract: An electronic system interconnect. The interconnect comprises a first node and a second node coupled to the first node. The interconnect is initially configured to include the first and second nodes. A third node is added to the interconnect after the interconnect is initially configured, and the first node responds to the addition of the third node by initiating a new connect handshake with the third node. The first node begins by transmitting a first signal to the third node. The first node signals that the third node has been added to the interconnect if the third node responds to the first signal by transmitting a second signal. The first node causes the interconnect to be reconfigured if the third node transmits a third signal in response to receiving the first signal.
    Type: Application
    Filed: July 18, 2005
    Publication date: November 10, 2005
    Inventors: William Duckwall, Michael Teener
  • Patent number: 5493570
    Abstract: An interface device for a point-to-point connected serial bus in which bus clock and bus data transmissions on the bus cease between transmissions of packets of data, includes a low latency resynchronizing circuit and an end of packet detector which is independent of control data within the packet. The resynchronizer is based on an interface which receives bus data and bus clock from a transmission of a packet on the bus. A circular input buffer stores bus data received from the bus in data locations indicated by an input pointer in response to the bus clock. An input pointer generator supplies the input pointers to the input buffer in a circular sequence, beginning in a particular location during a first bus clock in a packet. An output selector supplies bus data from one of the N data locations in the input buffer to the selector output in response to an output pointer and in response to the local clock.
    Type: Grant
    Filed: March 15, 1995
    Date of Patent: February 20, 1996
    Assignee: Apple Computer, Inc.
    Inventors: Daniel L. Hillman, Michael Teener
  • Patent number: 5400340
    Abstract: An interface device for a point-to-point connected serial bus in which bus clock and bus data transmissions on the bus cease between transmissions of packets of data, includes a low latency resynchronizing circuit and an end of packet detector which is independent of control data within the packet. The resynchronizer is based on an interface which receives bus data and bus clock from a transmission of a packet on the bus. A circular input buffer stores bus data received from the bus in data locations indicated by an input pointer in response to the bus clock. An input pointer generator supplies the input pointers to the input buffer in a circular sequence, beginning in a particular location during a first bus clock in a packet. An output selector supplies bus data from one of the N data locations in the input buffer to the selector output in response to an output pointer and in response to the local clock.
    Type: Grant
    Filed: March 4, 1993
    Date of Patent: March 21, 1995
    Assignee: Apple Computer, Inc.
    Inventors: Daniel L. Hillman, Michael Teener