Abstract: A parallelized or array method is developed for the generation of Reed Solomon parity bytes which utilizes multiple digital logic operations or computer instructions implemented using digital logic. At least one of the operations or instructions used performs the following combinations of steps: a) provide an operand representing N feedback terms where N is greater than one, b) computation of N by M Galios Field polynomial multiplications where M is greater than one, and c) computation of (N?1) by M Galios Field additions producing M result bytes. In this case the result bytes are used to modify the Reed Solomon parity bytes in either a separate operation or instruction or as part of the same operation. A parallelized or array method is also developed for the generation of Reed Solomon syndrome bytes which utilizes multiple digital logic operations or computer instructions implemented using digital logic.

Abstract: This application illustrates several techniques to incorporate AES hardware logic into a processor such that the AES operations are accessed as instructions of the processor. Once the AES operations are initiated by a processor instruction, they operate independently of the processor allowing the processor to perform other operations. In these implementations, the processor may perform other operations to save preceding data already processed by the AES operations. Also, the processor may perform other operations to prepare data for a subsequent AES operation. The AES hardware may have registers to buffer data results from a preceding AES operation so that the processor may read such data results after the AES hardware has initiated another operation. The AES hardware may also have registers to buffer data prepared for a subsequent AES operation so that the processor may prepare data for the following AES operation while the AES hardware is still completing a current operation.