Abstract: Examples disclosed herein relate to a on-chip or built-in self-test (BIST) module for an RFIC including means to up-convert a signal from a test frequency to RF at an input to the RFIC and down-convert and output signal.

Abstract: An interpolation circuit for comparing an input voltage signal with an interpolated reference signal derived from a first reference voltage signal and a second reference voltage signal may include a transconductive circuit configured to generate a first differential current signal proportional to a difference between the first reference voltage signal and the input voltage signal and a second differential current signal proportional to a difference between the second reference voltage signal and the input voltage signal, an intermediate circuit configured to generate a third differential current signal, and a transinductive circuit configured to generate an output voltage signal having a first polarity if a value of the input voltage signal is greater than a value of the interpolated reference signal and a second polarity if the value of the input signal is less than the value of the interpolated reference signal.

Abstract: Examples of systems and methods are provided for generating an output signal having an output code having less number of bits compared to an input signal having a thermometer code representation. The system may partition the input code bits into non-overlapping clusters. The system may generate a control signal for each of the clusters based on, at least in part, a logical OR operation over all bits in a corresponding one of the clusters. The system may determine a transition cluster comprising a 1/0 transition in the input code bits. The system may determine output code bits based on, at least in part, an input code bit pattern in the transition cluster and an identity of the transition cluster.

Abstract: An interpolation circuit for comparing an input voltage signal with an interpolated reference signal derived from a first reference voltage signal and a second reference voltage signal may include a transconductive circuit configured to generate a first differential current signal proportional to a difference between the first reference voltage signal and the input voltage signal and a second differential current signal proportional to a difference between the second reference voltage signal and the input voltage signal, an intermediate circuit configured to generate a third differential current signal, and a transinductive circuit configured to generate an output voltage signal having a first polarity if a value of the input voltage signal is greater than a value of the interpolated reference signal and a second polarity if the value of the input signal is less than the value of the interpolated reference signal.

Abstract: Examples of systems and methods are provided for generating an output signal having an output code having less number of bits compared to an input signal having a thermometer code representation. The system may partition the input code bits into non-overlapping clusters. The system may generate a control signal for each of the clusters based on, at least in part, a logical OR operation over all bits in a corresponding one of the clusters. The system may determine a transition cluster comprising a 1/0 transition in the input code bits. The system may determine output code bits based on, at least in part, an input code bit pattern in the transition cluster and an identity of the transition cluster.