Abstract: A memory device provides for a multiple-port read operation, and includes an array of bitcells and a control circuit. Each bitcell of the array includes a write wordline port and a first read wordline port. The control circuit provides an output to the write wordline port, and includes as inputs a write select port and a second read wordline port. In a write mode, the control circuit couples the write select port to the output and disables the second read port. In a read mode, the control circuit couples the second read wordline port to the output and disables the write select port, thereby enabling a multiple-port read operation to the array of bitcells.

Abstract: A memory device provides for a multiple-port read operation, and includes an array of bitcells and a control circuit. Each bitcell of the array includes a write wordline port and a first read wordline port. The control circuit provides an output to the write wordline port, and includes as inputs a write select port and a second read wordline port. In a write mode, the control circuit couples the write select port to the output and disables the second read port. In a read mode, the control circuit couples the second read wordline port to the output and disables the write select port, thereby enabling a multiple-port read operation to the array of bitcells.

Abstract: Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states of the group of memory cells, such that leakage parts are effectively eliminated. The memory array further includes logic for dynamically enabling a selected group of the memory cells during read or write access operations on the selected memory cells, wherein corresponding read or write bitlines are precharged before and after the respective rear or write operations.

Abstract: Systems and methods for detecting and improving writeability of a static random access memory (SRAM) cell. A bias voltage value corresponding to an operating condition, such as, a process, a voltage, or a temperature operation condition that indicates a cell write failure condition of an external SRAM array comprising the SRAM cell is generated. This bias voltage value is applied to word lines of SRAM cells in a model SRAM array. A first delay for a trigger signal rippled through the model SRAM array is detected and compared to a reference delay. A write assist indication is generated if the first delay is greater than or equal to the reference delay. Based on the write assist indication, a write assist is provided to the SRAM cell.

Abstract: Systems and methods for selectively boosting word-line (WL) voltage in a memory cell array. The method relies several embodiments to minimize energy costs associated with WL boost scheme. One embodiment generates a transient voltage boost rather than supply a DC voltage boost. The transient boost generation may be controlled on a cycle basis and can be disabled when the array is not accessed. Another embodiment allows the system to generate the transient voltage boost locally, near a WL driver and only during the cycles when it is needed. Localized boost voltage generation reduces the load capacitance that needs to be boosted to higher voltage. Another embodiment efficiently distributes the transient boost to the WL drivers.

Abstract: Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) in response to process-voltage-temperature variations when needed. Embodiments include a critical path that simulates a typical memory cell and read-out circuit in the SRAM. Applying a trigger signal to a word-line input port of the critical path, and comparing the output of the critical path to a reference-latch signal, provides an indication of when to boost the supply voltage to the read-out circuits of the SRAM.

Abstract: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.

Abstract: Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states of the group of memory cells, such that leakage parts are effectively eliminated. The memory array further includes logic for dynamically enabling a selected group of the memory cells during read or write access operations on the selected memory cells, wherein corresponding read or write bitlines are precharged before and after the respective rear or write operations.

Abstract: Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) in response to process-voltage-temperature variations when needed. Embodiments include a critical path that simulates a typical memory cell and read-out circuit in the SRAM. Applying a trigger signal to a word-line input port of the critical path, and comparing the output of the critical path to a reference-latch signal, provides an indication of when to boost the supply voltage to the read-out circuits of the SRAM.

Abstract: Systems and methods for detecting and improving writeability of a static random access memory (SRAM) cell. A bias voltage value corresponding to an operating condition, such as, a process, a voltage, or a temperature operation condition that indicates a cell write failure condition of an external SRAM array comprising the SRAM cell is generated. This bias voltage value is applied to word lines of SRAM cells in a model SRAM array. A first delay for a trigger signal rippled through the model SRAM array is detected and compared to a reference delay. A write assist indication is generated if the first delay is greater than or equal to the reference delay. Based on the write assist indication, a write assist is provided to the SRAM cell.

Abstract: Systems and methods for selectively boosting word-line (WL) voltage in a memory cell array. The method relies several embodiments to minimize energy costs associated with WL boost scheme. One embodiment generates a transient voltage boost rather than supply a DC voltage boost. The transient boost generation may be controlled on a cycle basis and can be disabled when the array is not accessed. Another embodiment allows the system to generate the transient voltage boost locally, near a WL driver and only during the cycles when it is needed. Localized boost voltage generation reduces the load capacitance that needs to be boosted to higher voltage. Another embodiment efficiently distributes the transient boost to the WL drivers.

Abstract: A sense amplifier circuit is implemented for suppressing Miller effect capacitive coupling. The amplifier circuit comprises a differential amplifier circuit having a first input, a first output interstitial node, a second input, a second output interstitial node, a third input to enable or disable the differential amplifier, and having an equalizer circuit coupled between the first output interstitial node and the second output interstitial node. The amplifier circuit also comprises a cross coupled latch circuit having a first latch input coupled to the first output interstitial node, a second latch input coupled to the second output interstitial node, a first latch output, and a second latch output, wherein during a first time period the first latch output and the second latch output are precharged, the differential amplifier circuit is disabled, and the equalizer circuit is enabled to suppress the Miller effect capacitive coupling on the sense amplifier inputs.

Abstract: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.

Abstract: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.

Abstract: A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance.

Abstract: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.

Abstract: The search key and key fields of a CAM in a cache are encoded with a Hamming distance of at least two to increase the speed of the CAM by ensuring each mismatching match line is discharged by at least two transistors in parallel. Where the cache is physically tagged, the search key is a physical address. The page address portion of the physical address is encoded prior to being stored in a TLB. The page offset bits are encoded in parallel with the TLB access, and concatenated with the encoded TLB entry. If a page address addresses a large memory page size, a plurality of corresponding sub-page addresses may be generated, each addressing a smaller page size. These sub-page addresses may be encoded and stored in a micro TLB. The encoded key and key field are tolerant of single-bit soft errors.

Abstract: Power consumption in a multi-level hierarchical Content Addressable Memory (CAM) circuit is reduced without adversely impacting performance. According to one embodiment of a multi-level hierarchical CAM circuit, the CAM circuit includes a plurality of lower-level match lines, a plurality of higher-level match lines and match line restoration circuitry. The lower-level match lines are configured to be restored to a pre-evaluation state during a pre-evaluation period. The higher-level match lines are configured to capture an evaluation state of respective groups of one or more of the lower-level match lines during an evaluation period and to be restored to a pre-evaluation state during the pre-evaluation period. The match line restoration circuitry is configured to prevent at least one of the lower-level match lines from being restored to the pre-evaluation state responsive to corresponding enable information, e.g., one or more bits indicating whether match line search results are to be utilized.

Abstract: Content Addressable Memory (CAM) search operations are aborted in response to a search abort signal, thus preserving previous CAM search results. In one embodiment, a CAM search operation is aborted by activating a local CAM match line in response to a search field provided to a CAM and preventing activation of a global CAM match line associated with the local CAM match line in response to a search abort signal. By preventing activation of global CAM match lines, monotonic storage devices included in a holding register that captures CAM search results are prevented from overwriting previously stored CAM search results.

Abstract: A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance.