Abstract: A divider includes a digit recoder that recodes upper bits of a partial remainder into sets of lower-radix multiples without carry propagate addition. Elimination of the carry propagate adder makes computation of the quotient carry free and independent of the number of bits computed per cycle, thereby enabling a higher number of bits per cycle, as well as increased clock speeds.

Abstract: A floating-point (FP) arithmetic unit includes a first FP execution pipeline operatively coupled to a register file, the first FP execution pipeline configured to perform a first FP operation on a first FP operand provided by the register file, the first FP execution pipeline comprising a plurality of execution units; and a first normalization unit operatively coupled to the register file, and the first FP execution pipeline, the first normalization unit configured to normalize the first FP operand, wherein the first normalization unit is configured to operate in parallel with the first FP execution pipeline, and is further configured to, in response to detecting that the first FP operand is a denormal, assert a first FP execution pipeline busy flag to stall the instruction dispatch of a first subsequent FP operation, the first FP operation and the first subsequent FP operation being of one FP operation type.

Abstract: Systems and methods relate to division of a dividend by a divisor, with fast result formatting. Counts of leading sign bits of the dividend and the divisor are determined. The dividend and the divisor are normalized based on their respective counts of leading sign bits to obtain a normalized dividend and a normalized divisor, respectively. An exact number of significant quotient bits of a quotient of the division, based on the normalized dividend, the normalized divisor, and the counts of leading sign bits of the dividend and the divisor and used to determine a correct position of a leading bit of the quotient based on this exact number. The quotient is developed by placing the leading bit at or near the correct position and appending less significant bits to the right of the leading bit. Thus, left-shifts in each iteration and large final shifts are avoided in formatting the result.

Abstract: Systems and methods relate to a division/root computation unit. A lookup table according to a Sweeney, Robertson, and Tocher (SRT) algorithm for a division/root computation is stored in a memory. Information related to a selected column corresponding to a divisor/root estimate is stored in a high-speed memory. Division/root computation is performed iteratively using the cached information to improve access times and reduce latency of accessing the entire lookup table on each iteration. In each iteration, a quotient/root is determined from the cached information based on a current partial remainder, and a next partial remainder is generated based on the quotient/root, the divisor/root estimate, and the current partial remainder.

Abstract: Systems and methods relate to division of a dividend by a divisor, with fast result formatting. Counts of leading sign bits of the dividend and the divisor are determined. The dividend and the divisor are normalized based on their respective counts of leading sign bits to obtain a normalized dividend and a normalized divisor, respectively. An exact number of significant quotient bits of a quotient of the division, based on the normalized dividend, the normalized divisor, and the counts of leading sign bits of the dividend and the divisor and used to determine a correct position of a leading bit of the quotient based on this exact number. The quotient is developed by placing the leading bit at or near the correct position and appending less significant bits to the right of the leading bit. Thus, left-shifts in each iteration and large final shifts are avoided in formatting the result.

Abstract: Presented is a “high-order” Leading Zeros Anticipator or LZA circuit and specifically a five-input LZA. The prior-art two-input LZA circuit is part of almost all high-performance floating-point units or FPUs. The advantages of a high-order LZA (such as five-input) is that the LZA function may be started and finished sooner in the floating point pipeline, and therefore allows more time for other functions in the pipeline. Therefore, a high-order LZA, such as five-input LZA, may be faster than the prior art two-input LZA designs. Thus, speeding up the LZA function in a floating point pipeline may significantly increase the speed in which the overall floating-point unit may operate as compared to the prior-art two input LZA designs and may additionally inspire new floating-point michroarchitectures which may yield further performance gains.

Abstract: An apparatus for generating an end-around carry to an end-around carry adder in a floating-point pipeline within a computer system is disclosed. The apparatus for generating an end-around carry includes a shift-comparison logic circuit, a sign-comparison circuit, and a logic gate. The shift-comparison logic circuit produces a shift-count signal and the sign-comparison logic circuit produces an effective operation signal. Coupled to the shift-comparison logic circuit and the sign-comparison logic circuit, the logic gate combines the shift-count signal and the effective operation signal with a carry-out signal generated by an end-around carry adder to provide an end-around carry signal for the end-around carry adder.