Abstract: Programmable delay circuits are described herein according to embodiments of the present disclosure. In one embodiment, a delay circuit comprises a plurality of delay stages coupled in series. Each of the delay stages comprises a delay gate on a forward path of the delay circuit, wherein the delay gate is configured to pass or block a signal on the forward path depending on a logic state of a respective select signal. Each of the delay stages also comprises a multiplexer on a return path of the delay circuit, wherein the multiplexer is configured to pass a signal on the return path or route the signal on the forward path to the return path depending on the logic state of the respective select signal. Output logic states of the delay gates and the multiplexers may remain static during a change in the delay setting of the delay circuit to reduce glitch.

Abstract: Programmable delay circuits are described herein according to embodiments of the present disclosure. In one embodiment, a delay circuit comprises a plurality of delay stages coupled in series. Each of the delay stages comprises a delay gate on a forward path of the delay circuit, wherein the delay gate is configured to pass or block a signal on the forward path depending on a logic state of a respective select signal. Each of the delay stages also comprises a multiplexer on a return path of the delay circuit, wherein the multiplexer is configured to pass a signal on the return path or route the signal on the forward path to the return path depending on the logic state of the respective select signal. Output logic states of the delay gates and the multiplexers may remain static during a change in the delay setting of the delay circuit to reduce glitch.

Abstract: A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with a first set of modules to a second power mode corresponding to the desired operational frequency and associated with a second set of modules. The apparatus enables modules in the second set of modules that are unassociated with the first power mode, stops traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode, routes traffic through the second set of modules, and disables modules in the first set of modules that are unassociated with the second power mode.

Abstract: A device comprising a clock circuit, a control circuit, and a current mode logic (CML) circuit is disclosed. The clock circuit provides a first differential clock signal and the control circuit generates a control signal based at least in part on the frequency of the first differential clock signal. The CML circuit generates a second differential clock signal based at least in part on the first differential clock signal. The CML circuit operates in one of a plurality of different frequency modes based at least in part on the control signal and includes a number of variable resistors that are responsive to the control signal.

Abstract: A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.

Abstract: A device comprising a clock circuit, a control circuit, and a current mode logic (CML) circuit is disclosed. The clock circuit provides a first differential clock signal and the control circuit generates a control signal based at least in part on the frequency of the first differential clock signal. The CML circuit generates a second differential clock signal based at least in part on the first differential clock signal. The CML circuit operates in one of a plurality of different frequency modes based at least in part on the control signal and includes a number of variable resistors that are responsive to the control signal.

Abstract: A delay architecture for reducing downtime during frequency switching is described herein. In one embodiment, an adjustable delay circuit comprises a phase-locked loop (PLL) or a delay-locked loop (DLL) configured to generate a bias voltage, and a plurality of delay elements coupled in series, wherein each of the delay elements is biased by the bias voltage. The adjustable delay circuit also comprises a multiplexer coupled to outputs of two or more of the delay elements, wherein each of the outputs corresponds to a different delay of an input signal, and wherein the multiplexer is configured to select one of the outputs based on a data frequency of a memory interface.

Abstract: Techniques for reducing cross-supply current are described herein. In one embodiment, a power circuit comprises a bypass switch coupled between a first power supply and an internal power supply, and a voltage regulator coupled between a second power supply and the internal power supply. The power circuit also comprises a shut-off circuit configured to detect the first power supply powering up before the second power supply during a power-up sequence, to shut off the bypass switch upon detecting the first power supply powering up before the second power supply, to detect the second power supply powering up during the power-up sequence, and to release control of the bypass switch to a controller upon detecting the second power supply powering up.

Abstract: A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.

Abstract: A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with a first set of modules to a second power mode corresponding to the desired operational frequency and associated with a second set of modules. The apparatus enables modules in the second set of modules that are unassociated with the first power mode, stops traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode, routes traffic through the second set of modules, and disables modules in the first set of modules that are unassociated with the second power mode.