Abstract: In a particular embodiment using a distributed architecture, the electronic device comprises a source memory means partitioned in N elementary source memories for storing a sequence of input data, processing means clocked by a clock signal and having N outputs for producing per cycle of the clock signal N data respectively associated to N input data respectively stored in the N elementary source memories at relative source addresses, N single port target memories, N interleaving tables containing for each relative source address the number of one target memory and the corresponding relative target address therein, N cells connected in a ring structure, each cell being further connected between one output of the processing means, one interleaving table, and the port of one target memory, each cell being adapted to receive data from said output of the processing means and from its two neighbouring cells or to write at least some of these received data sequentially in the associated target memory, in accordance

Abstract: Methods and apparatus wherein subsequent permutation and inverse permutation operations provide inputs in correct order for first and second processes. Processes needing inputs in original order and processes needing inputs in permutated order can be distinguished, thereby using one of the processes as reference process. Permutation and inverse permutation operations which can fit into a turbo coding system and in systems applying the turbo coding principle. At least one permutation and one inverse permutation operation can be performed subsequently. Permutation and inverse permutation operations may be altered by scheduling linear writing and reading operation and permutated or inverse permutated writing and reading operations. These methods enable parallel execution of sub-processes, where the processes producing and consuming data can be performed in a parallel way, and the writing and reading operations to and from a memory can be performed in a parallel way.

Abstract: Methods and apparatus are described wherein subsequent permutation and inverse permutation operations provide inputs in correct order for first and second processes. Processes needing inputs in original order and processes needing inputs in permutated order can be distinguished, thereby using one of said processes as reference process. Permutation and inverse permutation operations are described which can fit into a turbo coding system and in systems applying the turbo coding principle. At least one permutation and one inverse permutation operation can be performed subsequently. Permutation and inverse permutation operations may be altered by scheduling linear writing and reading operations and permutated or inverse permutated writing and reading operations. These methods enable parallel execution of sub-processes, where the processes producing and consuming data can be performed in a parallel way, and the writing and the reading operations to and from a memory can be performed in a parallel way.