Patents by Inventor Michael Tian

Michael Tian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10909293
    Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 2, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wangyang Zhang, Hongzhou Liu, Richard J. O'Donovan, Michael Tian
  • Patent number: 10853550
    Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: December 1, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wangyang Zhang, Hongzhou Liu, Richard J. O'Donovan, Michael Tian
  • Patent number: 10395000
    Abstract: Various embodiments implement an electronic design with one or more electrical analyses or simulations. Pre-layout and/or post-layout design data of an electronic design or a portion thereof may be identified at a physical design implementation module. A first stage analysis may be performed on the electronic design or the portion thereof at least by computing electrical characteristics with a reduced representation in the electronic design or the portion thereof. Electrical behavior of the electronic design or the portion thereof may be generated at least by performing a second stage analysis on the electronic design or the portion thereof with one or more adjusted electrical characteristics. The electronic design or the portion thereof may then be implemented based in part or in whole upon the one or more electrical analyses or simulations.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: August 27, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: John Yanjiang Shu, Wei Michael Tian, Richard J. O'Donovan
  • Patent number: 10216887
    Abstract: Various embodiments implement an electronic design with power gate analyses using time varying resistors. Design data of an electronic design or a portion thereof may be identified at an electronic design implementation module. First stage electrical characteristics may be generated at least by performing a first stage electrical analysis on a reduced representation of the electronic design or the portion thereof. Second stage electrical characteristics may further be generated at least by performing a second stage electrical analysis on a parasitic injected representation of the electronic design or the portion thereof with a time-varying model for the power gate. The electronic design or the portion thereof may then be further implemented based in part or in whole upon the one or more electrical analyses or simulations.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 26, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: John Yanjiang Shu, Wei Michael Tian, Richard J. O'Donovan
  • Patent number: 9579204
    Abstract: A method of constructing a surgical implant is provided. The method comprises providing a multiplicity of substantially identical blocks, each having features thereon to allow blocks to be mechanically joined together. A surgical implant may then be constructed by using these features to join the blocks together into a desired configuration.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: February 28, 2017
    Assignee: OXFORD MESTAR LIMITED
    Inventors: Zhanfeng Cui, Phillipus Johannes Putter, Michael Tian-Ao Cui
  • Publication number: 20170007406
    Abstract: A method of constructing a surgical implant is provided. The method comprises providing a multiplicity of substantially identical blocks, each having features thereon to allow blocks to be mechanically joined together. A surgical implant may then be constructed by using these features to join the blocks together into a desired configuration.
    Type: Application
    Filed: July 10, 2015
    Publication date: January 12, 2017
    Inventors: Zhanfeng CUI, Phillipus Johannes PUTTER, Michael Tian-Ao CUI
  • Patent number: 8954908
    Abstract: A system, method, and computer program product for automatically approximating conventional Monte Carlo statistical device model evaluation for circuit simulation with drastic speed improvements, while preserving significant accuracy. Embodiments enable quick inspection of the effects of process mismatch variations on single devices and even large circuits compared to standard computationally prohibitive Monte Carlo analysis. Statistical device model variation is calculated as if all such variation is due to changes in threshold voltage, even though other physical phenomena are known to contribute. Threshold voltage variation is modeled as a function of statistical variation, device size, and working bias condition. Circuit simulation is faster when the full internal device model parameter set is not rebuilt for every Monte Carlo analysis iteration. Embodiments are compatible with both conventional SPICE and newer Fast SPICE simulations.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: February 10, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hongzhou Liu, Jushan Xie, Michael Tian, An-Chang Deng
  • Patent number: 8954917
    Abstract: A system, method, and computer program product is disclosed for performing electrical analysis of a circuit design. A voltage-based approach is described for performing two-stage transient EM-IR drop analysis of an electronic design. A two-stage approach is performed in some embodiments, in which the first stage operates by calculating the voltage at certain interface nodes. In the second stage, simulation is performed to simulate the circuit to concurrently obtain the current at the interface nodes. In some embodiments, multiple adjacent devices as identified as interface devices for purposes of the analysis. One situation where it may be useful to analyze a larger portion of the circuitry in this way where the analysis is being performed on a netlist having a power gate.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: February 10, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: John Yanjiang Shu, Wei Michael Tian, An-Chang Deng