Abstract: The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method execute similar portions of a test segment on a known device, i.e., a device for which it has been determined that the test segment executes successfully, and on a device-under-test (DUT), i.e., a device for which it has been determined that the test segment does not execute successfully. The results of the tests are compared to determine if the test passed or failed. The test segment is executed iteratively on the known device and the DUT, increasing or decreasing the amount of the test segment that is executed each pass until the failing instruction is identified.

Abstract: In an LSSD/LBIST scan design, AC scan test coverage is enhanced with a scan chain configuration capable of selectively inverting scan-in signals. For example, one or more XOR gates are inserted in the scan chain. The XOR gates is controlled by a control signal preferably coming from a primary input such that original scan-in signals as well as inverted scan-in signals are shifted into the scan chain. The proposed configuration significantly enhances the AC test coverage for a scan chain having adjacent SRLs feeding the same cone of logic by adding a simple logic circuit such as an XOR gate between the adjacent SRLs.

Abstract: An apparatus and a method for testing one or more processors. The apparatus and method provide a host computer that issues test case information. The test case information is translated from the architecture used by a host computer to the architecture required by the electronic components. The processors are then able to perform the test case.

Abstract: The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method provide a CRC function that is used to calculate a CRC value for a portion of memory. The CRC value is compared with an expected CRC value to determine if the electrical component passed or failed the test.

Abstract: The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method execute similar portions of a test segment on a known device, i.e., a device for which it has been determined that the test segment executes successfully, and on a device-under-test (DUT), i.e., a device for which it has been determined that the test segment does not execute successfully. The results of the tests are compared to determine if the test passed or failed. The test segment is executed iteratively on the known device and the DUT, increasing or decreasing the amount of the test segment that is executed each pass until the failing instruction is identified.

Abstract: In an LSSD/LBIST scan design, AC scan test coverage is enhanced with a scan chain configuration capable of selectively inverting scan-in signals. For example, one or more XOR gates are inserted in the scan chain. The XOR gates is controlled by a control signal preferably coming from a primary input such that original scan-in signals as well as inverted scan-in signals are shifted into the scan chain. The proposed configuration significantly enhances the AC test coverage for a scan chain having adjacent SRLs feeding the same cone of logic by adding a simple logic circuit such as an XOR gate between the adjacent SRLs.

Abstract: An apparatus and a method for testing one or more processors. The apparatus and method provide a host computer that issues test case information. The test case information is translated from the architecture used by a host computer to the architecture required by the electronic components. The processors are then able to perform the test case.

Abstract: The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method provide a CRC function that is used to calculate a CRC value for a portion of memory. The CRC value is compared with an expected CRC value to determine if the electrical component passed or failed the test.