Abstract: A cache system provides for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses and for responding to slot MRU misses and cache misses. An N-way set associative cache is provided, each set of said cache including an SRAM array macro having a memory element, an internal SRAM data register, and a read enable signal line. Read enable is generated as the NOR of slot miss and cache miss signals, and the internal SRAM data register is responsive to the slot miss signal for registering data output during a first cycle for use in a next following cycle.