Abstract: The present invention relates to a method of joining glass elements with material continuity, to a glass component, to a housing, and to a vacuum insulating panel. The method comprises the following steps providing first and second glass elements, with each of the glass elements having at least one joining region having an outer edge to be joined, introducing a metallic material into the first glass element in the region of the joining region of the first glass element, placing the first and second glass elements onto one another such that the first and second glass elements contact one another at least at one outer edge of the respective joining region; and heating the metallic material in the first glass element so that the glass element at least partially melts in the region of the joining region of the first glass element so that a connection with material continuity is produced between the first and second glass elements.

Abstract: A method for manufacturing an electronic component can include the following steps: providing a semiconductor arrangement comprising a carrier structure which has at least one semiconductor chip incorporated into a potting compound, and a redistribution layer which comprises a flexible material and at least one strip conductor, wherein the carrier structure at least in regions is connected to the redistribution layer, and the at least one semiconductor chip is electrically conductively connected to the redistribution layer, and separating the carrier structure along at least one trench in a manner such that the carrier structure is divided into at least two singularized carrier elements, wherein two adjacent ones of the singularized carrier elements are connected to one another over the respective trench by way of the redistribution layer.

Abstract: The present invention relates to a bonding method for connecting a first wafer and a second wafer, wherein firstly a first adhesive layer is deposited onto a surface of the first wafer. Furthermore, a second adhesive layer is deposited onto the first adhesive layer, and the two adhesive layers are structured by way of selective removal of both adhesive layers in at least one predefined region of the first wafer, Moreover, the first wafer is connected to the second wafer by way of pressing a surface of the second wafer onto the second adhesive layer, wherein the second adhesive layer is more flowable that the first adhesive layer on connecting the first wafer to the second wafer.

Abstract: The present invention relates to a bonding method for connecting a first wafer and a second wafer, wherein firstly a first adhesive layer is deposited onto a surface of the first wafer. Furthermore, a second adhesive layer is deposited onto the first adhesive layer, and the two adhesive layers are structured by way of selective removal of both adhesive layers in at least one predefined region of the first wafer, Moreover, the first wafer is connected to the second wafer by way of pressing a surface of the second wafer onto the second adhesive layer, wherein the second adhesive layer is more flowable that the first adhesive layer on connecting the first wafer to the second wafer.

Abstract: A method for manufacturing an electronic component can include the following steps: providing a semiconductor arrangement comprising a carrier structure which has at least one semiconductor chip incorporated into a potting compound, and a redistribution layer which comprises a flexible material and at least one strip conductor, wherein the carrier structure at least in regions is connected to the redistribution layer, and the at least one semiconductor chip is electrically conductively connected to the redistribution layer, and separating the carrier structure along at least one trench in a manner such that the carrier structure is divided into at least two singularized carrier elements, wherein two adjacent ones of the singularized carrier elements are connected to one another over the respective trench by way of the redistribution layer.

Abstract: The invention relates to a component arrangement with a first substrate and at least one second substrate arranged on the first substrate, wherein the first substrate has at least one first contact element and the at least one second substrate has at least one second contact element and the contact elements each has a contact surface connected such as to give an electrical contact and a protective layer connecting the first and second substrate together. During production the protective layer is structured such that a part surface of the first substrate and a part surface of the at least one second substrate are not covered, wherein the part surfaces include the contact surfaces of the at least one first and second contact elements and the contact generated between the contact surfaces is hence not contaminated by the protective layer. The contact surfaces are thus freely accessible without elements of the protective layer lying therebetween.

Abstract: An in-vivo implantable coil assembly includes a planar coil having at least one coil layer formed from conductive traces disposed in or on a polymer matrix. A ferrite platelet is bonded to a surface of the polymer matrix. Methods of making and using the in-vivo implantable coil assembly are also disclosed.

Abstract: The invention relates to a component arrangement with a first substrate and at least one second substrate arranged on the first substrate, wherein the first substrate has at least one first contact element and the at least one second substrate has at least one second contact element and the contact elements each has a contact surface connected such as to give an electrical contact and a protective layer connecting the first and second substrate together. During production the protective layer is structured such that a part surface of the first substrate and a part surface of the at least one second substrate are not covered, wherein the part surfaces include the contact surfaces of the at least one first and second contact elements and the contact generated between the contact surfaces is hence not contaminated by the protective layer. The contact surfaces are thus freely accessible without elements of the protective layer lying therebetween.

Abstract: Interconnect metallization schemes and devices for flip chip bonding are disclosed and described. Metallization schemes include an adhesion layer, a diffusion barrier layer, a wetable layer, and a wetting stop layer. Various thicknesses and materials for use in the different layers are disclosed and are particularly useful for metallization in implantable electronic devices such as neural electrode arrays.