Patents by Inventor Michael Tooher
Michael Tooher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8416633Abstract: A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of VDD?(1.5*Vth), or maintain 1.5*Vth across the memory cells, where Vth is a threshold voltage of an SRAM memory cell transistor and VDD is a positive supply voltage. By tracking the Vth of the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.Type: GrantFiled: November 8, 2011Date of Patent: April 9, 2013Assignee: Mosaid Technologies IncorporatedInventors: Michael Anthony Zampaglione, Michael Tooher
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Publication number: 20120057416Abstract: A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of VDD?(1.5*Vth), or maintain 1.5*Vth across the memory cells, where Vth is a threshold voltage of an SRAM memory cell transistor and VDD is a positive supply voltage. By tracking the Vth of the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.Type: ApplicationFiled: November 8, 2011Publication date: March 8, 2012Inventors: Michael Anthony ZAMPAGLIONE, Michael TOOHER
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Patent number: 8077527Abstract: A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of VDD?(1.5*Vth), or maintain 1.5*Vth across the memory cells, where Vth is a threshold voltage of an SRAM memory cell transistor and VDD is a positive supply voltage. By tracking the Vth of the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.Type: GrantFiled: February 12, 2010Date of Patent: December 13, 2011Assignee: Mosaid Technologies IncorporatedInventors: Michael Anthony Zampaglione, Michael Tooher
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Publication number: 20100232236Abstract: A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of VDD?(1.5*Vth), or maintain 1.5*Vth across the memory cells, where Vth is a threshold voltage of an SRAM memory cell transistor and VDD is a positive supply voltage. By tracking the Vth of the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.Type: ApplicationFiled: February 12, 2010Publication date: September 16, 2010Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventors: Michael Anthony ZAMPAGLIONE, Michael TOOHER
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Publication number: 20100142298Abstract: An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on the ASIC chip outside of the memory instances. The control block has a defective memory register for storing an address of a defective memory subunit. The address of a defective memory subunit from the defective memory register in the control block is transferred to the universal interface register in the memory instance. In one embodiment, the control block includes fuses for storing a defective subunit address in binary form. A fuse array is located outside of the memory instances and contains laser fuses that represent address of defective subunits for each memory instance.Type: ApplicationFiled: February 5, 2010Publication date: June 10, 2010Inventor: Michael Tooher
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Patent number: 7684262Abstract: A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of Vdd?(1.5*Vth), or maintain 1.5*Vth across the memory cells, where Vth is a threshold voltage of an SRAM memory cell transistor and VDD is a positive supply voltage. By tracking the Vth of the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.Type: GrantFiled: April 27, 2007Date of Patent: March 23, 2010Assignee: Mosaid Technologies IncorporatedInventors: Michael Anthony Zampaglione, Michael Tooher
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Patent number: 7460413Abstract: An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on the ASIC chip outside of the memory instances. The control block has a defective memory register for storing an address of a defective memory subunit. The address of a defective memory subunit from the defective memory register in the control block is transferred to the universal interface register in the memory instance. In one embodiment, the control block includes fuses for storing a defective subunit address in binary form. A fuse array is located outside of the memory instances and contains laser fuses that represent address of defective subunits for each memory instance.Type: GrantFiled: August 31, 2006Date of Patent: December 2, 2008Inventor: Michael Tooher
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Publication number: 20070252623Abstract: A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of Vdd?(1.5*Vth), or maintain 1.5*Vth across the memory cells, where Vth is a threshold voltage of an SRAM memory cell transistor and VDD is a positive supply voltage. By tracking the Vth of the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.Type: ApplicationFiled: April 27, 2007Publication date: November 1, 2007Applicant: MOSAID TECHNOLOGIES CORPORATIONInventors: Michael Zampaglione, Michael Tooher
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Publication number: 20070113208Abstract: An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on the ASIC chip outside of the memory instances. The control block has a defective memory register for storing an address of a defective memory subunit. The address of a defective memory subunit from the defective memory register in the control block is transferred to the universal interface register in the memory instance. In one embodiment, the control block includes fuses for storing a defective subunit address in binary form. A fuse array is located outside of the memory instances and contains laser fuses that represent address of defective subunits for each memory instance.Type: ApplicationFiled: August 31, 2006Publication date: May 17, 2007Inventor: Michael Tooher
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Patent number: 7154792Abstract: An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on the ASIC chip outside of the memory instances. The control block has a defective memory register for storing an address of a defective memory subunit. The address of a defective memory subunit from the defective memory register in the control block is transferred to the universal interface register in the memory instance. In one embodiment, the control block includes fuses for storing a defective subunit address in binary form. A fuse array is located outside of the memory instances and contains laser fuses that represent address of defective subunits for each memory instance.Type: GrantFiled: May 8, 2006Date of Patent: December 26, 2006Inventor: Michael Tooher
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Publication number: 20060203582Abstract: An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on the ASIC chip outside of the memory instances. The control block has a defective memory register for storing an address of a defective memory subunit. The address of a defective memory subunit from the defective memory register in the control block is transferred to the universal interface register in the memory instance. In one embodiment, the control block includes fuses for storing a defective subunit address in binary form. A fuse array is located outside of the memory instances and contains laser fuses that represent address of defective subunits for each memory instance.Type: ApplicationFiled: May 8, 2006Publication date: September 14, 2006Inventor: Michael Tooher
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Patent number: 7046561Abstract: An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on the ASIC chip outside of the memory instances. The control block has a defective memory register for storing an address of a defective memory subunit. The address of a defective memory subunit from the defective memory register in the control block is transferred to the universal interface register in the memory instance. In one embodiment, the control block includes fuses for storing a defective subunit address in binary form. A fuse array is located outside of the memory instances and contains laser fuses that represent address of defective subunits for each memory instance.Type: GrantFiled: April 16, 2003Date of Patent: May 16, 2006Inventor: Michael Tooher
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Patent number: 6380592Abstract: A semiconductor memory cell that includes a word line, two bit lines, a precharge line, and two cross-coupled inverters. Each of the inverters is formed by a P-channel transistor and an N-channel transistor. Additionally, a first access transistor selectively couples one bit line to the output of one inverter, and a second access transistor selectively couples the other bit line to the output of the other inverter. One terminal of the N-channel transistor of each of the inverters is connected to the precharge line. In a preferred embodiment, the access transistors are P-channel transistors and the gate terminal of each PMOS access transistor is connected to the word line. Additionally, the present invention provides a method of writing data to a semiconductor memory cell that is connected to a pair of bit lines.Type: GrantFiled: November 25, 1998Date of Patent: April 30, 2002Assignee: STMicroelectronics S.r.l.Inventors: Michael Tooher, Stefano Tonello
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Publication number: 20020003244Abstract: A semiconductor memory cell that includes a word line, two bit lines, a precharge line, and two cross-coupled inverters. Each of the inverters is formed by a P-channel transistor and an N-channel transistor. Additionally, a first access transistor selectively couples one bit line to the output of one inverter, and a second access transistor selectively couples the other bit line to the output of the other inverter. One terminal of the N-channel transistor of each of the inverters is connected to the precharge line. In a preferred embodiment, the access transistors are P-channel transistors and the gate terminal of each PMOS access transistor is connected to the word line. Additionally, the present invention provides a method of writing data to a semiconductor memory cell that is connected to a pair of bit lines.Type: ApplicationFiled: November 25, 1998Publication date: January 10, 2002Inventors: MICHAEL TOOHER, STEFANO TONELLO
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Patent number: 6229746Abstract: The invention relates to a pulse generator circuitry for timing a low-power memory device of a type associated to a memory matrix, including a plurality of word lines driven by a row decoder, and a plurality of bit lines sensed by sense amplifiers. The matrix includes at least a dummy row and at least one dummy column. A delay chain of the pulse generator is formed by the dummy datapath of the memory matrix. The dummy datapath being defined by at least on dummy row and at least one dummy column. The datapath operates prior to the operation of the normal row and column path of the matrix. In another embodiment disclosed, the row decoder comprises a dummy row enable portion at the intersection between the dummy row and the dummy column. The delay chain includes at least the dummy row enable portion, the dummy row and the dummy column.Type: GrantFiled: July 29, 1999Date of Patent: May 8, 2001Assignee: STMicroelectronics S.r.l.Inventor: Michael Tooher
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Patent number: 6160730Abstract: The invention relates to a memory comprising memory cells arranged in continuous rows which are divided in at least two subrows separately selectable by a row decoder through respective word selection metallizations. Each word selection metallization extends over the row containing the corresponding subrow and the subrows of each row are interlaced.Type: GrantFiled: April 10, 1997Date of Patent: December 12, 2000Assignee: STMicroelectronics, S.r.l.Inventor: Michael Tooher
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Patent number: 5463630Abstract: A method of converting a parallel, time-division-multiplexed data stream into individual serial data streams wherein the individual parallel data words are written in parallel into and read serially from one of a plurality of buffers, wherein each parallel data word is presented simultaneously to the parallel inputs of all buffers, and that for each data word, the inputs of only one buffer are enabled. Also a converter for converting two or more individual serial data streams into a single parallel, time-division-multiplexed data stream, having one buffer per serial data stream which can be written into serially and read from in parallel, wherein all buffers are connected in parallel at the output end, that the outputs of each buffer can be enabled, and that a decoding device is provided on the parallel side which makes it possible to enable the outputs of one buffer at a time.Type: GrantFiled: July 12, 1994Date of Patent: October 31, 1995Assignee: Alcatel N.V.Inventor: Michael Tooher