Abstract: The present disclosure relates to a biocompatible, in vitro probe system. The probe system may have a substrate and a culture well supported on the substrate. The culture well defines a three-dimensional volume for containing in vitro cultures of electroactive cells. The probe system has at least one probe subsystem supported on the substrate. The probe subsystem has at least one probe having an array of electrodes, with the probe being disposed within the culture well for in vitro electrically communicating with the electroactive cells. The probe subsystem is adapted to be interfaced to an external instrumentation/recording device.

Abstract: The present disclosure relates to a biocompatible, in vitro probe system. The probe system may have a substrate and a culture well supported on the substrate. The culture well defines a three-dimensional volume for containing in vitro cultures of electroactive cells. The probe system has at least one probe subsystem supported on the substrate. The probe subsystem has at least one probe having an array of electrodes, with the probe being disposed within the culture well for in vitro electrically communicating with the electroactive cells. The probe subsystem is adapted to be interfaced to an external instrumentation/recording device.

Abstract: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.

Abstract: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.

Abstract: A semiconductor wafer structure. The structure comprises a plurality of semiconductor wafers. The plurality of semiconductor wafers comprises a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer is located adjacent to the second semiconductor wafer such that no additional wafers of the plurality of semiconductor wafers is located between a topside of the first semiconductor wafer and a backside of the of the second semiconductor wafer. A relationship is provided between a plurality of values for an electrical characteristic and a plurality of materials. A substructure is formed comprising a material from the plurality of materials existing in the relationship sandwiched between a topside of the first semiconductor wafer and a backside of the of the second semiconductor wafer. The first semiconductor wafer comprises a discrete value from the plurality of values for the electrical characteristic that correlates with the material in said relationship.

Abstract: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.

Abstract: A structure and fabrication method for a gate stack used to define source/drain regions in a semiconductor substrate. The method comprises (a) forming a gate dielectric layer on top of the substrate, (b) forming a gate polysilicon layer on top of the gate dielectric layer, (c) implanting n-type dopants in a top layer of the gate polysilicon layer, (d) etching away portions of the gate polysilicon layer and the gate dielectric layer so as to form a gate stack on the substrate, and (e) thermally oxidizing side walls of the gate stack with the presence of a nitrogen-carrying gas. As a result, a diffusion barrier layer is formed at the same depth in the polysilicon material of the gate stack regardless of the doping concentration. Therefore, the n-type doped region of the gate stack has the same width as that of the undoped region of the gate stack.

Abstract: A method and structure for fabricating semiconductor wafers. The method comprises providing a plurality of semiconductor wafers. The plurality of semiconductor wafers comprises a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer is located adjacent to the second semiconductor wafer. A relationship is provided between a plurality of values for an electrical characteristic and a plurality of materials. A material is chosen from the plurality of materials existing in the relationship. A substructure is formed comprising the material sandwiched between a topside of the first semiconductor wafer and a backside of a portion of the of the second semiconductor wafer. The plurality of semiconductor wafers are placed into a furnace comprising an elevated temperature for processing resulting in a value for the first semiconductor wafer of the electrical characteristic that corresponds to said material in said relationship.