Abstract: A storage system includes circuitry and memory cells that are coupled to multiple WLs and to multiple BLs. The circuitry includes combinational logic, and is configured to: set a read voltage to a target WL, and set each of the other WLs, including a neighbor WL neighboring to the target WL, to a predefined full conducting voltage or to a predefined partial conducting voltage lower than the full conducting voltage, pre-charge the BLs, and while discharging the BLs, read a page from a group of target memory cells multiple times, to produce multiple respective binary readouts, at least one of the readouts corresponds to setting the neighbor WL to the partial conducting voltage, apply the combinational logic to the readouts to produce (i) output bits of the page, and (ii) confidence levels associated with the output bits, and transmit the output bits and the confidence levels to a controller.

Abstract: An apparatus for data storage includes circuitry and a plurality of memory cells. The memory cells are coupled to word lines (WLs), and are configured to store data values in respective predefined programming levels. The circuitry is configured to: receive data values for storage in the memory cells of a given WL, select memory cells of the given WL that are to store a given data value among the received data values, set a verification voltage for programming the selected memory cells, so that a difference between the verification voltage and a read voltage predetermined for the selected memory cells depends on a rate of drift that is expected to occur to a threshold voltage distribution associated with the selected memory cells when programmed, apply one or more programming pulses to the given WL, and verify that the selected memory cells have been programmed successfully using the set verification voltage.

Abstract: A storage system includes circuitry and memory cells that are coupled to multiple WLs and to multiple BLs. The circuitry includes combinational logic, and is configured to: set a read voltage to a target WL, and set each of the other WLs, including a neighbor WL neighboring to the target WL, to a predefined full conducting voltage or to a predefined partial conducting voltage lower than the full conducting voltage, pre-charge the BLs, and while discharging the BLs, read a page from a group of target memory cells multiple times, to produce multiple respective binary readouts, at least one of the readouts corresponds to setting the neighbor WL to the partial conducting voltage, apply the combinational logic to the readouts to produce (i) output bits of the page, and (ii) confidence levels associated with the output bits, and transmit the output bits and the confidence levels to a controller.

Abstract: A controller includes an interface and circuitry. The interface is coupled to multiple memory cells. The circuitry stores a code word in a group of the memory cells, reads the code word using different thresholds to produce first and second readouts, and checks whether approximating each of first and second numbers of readout errors based on syndrome weights is valid. In response to determining that only the approximation of the second number of errors is valid, the circuitry produces a combined readout by replacing a portion of the bits in the second readout with corresponding bits of the first readout, calculates an enhanced syndrome weight for the combined readout and estimates the first number of errors based on the enhanced syndrome weight. The circuitry improves readout performance from at least the group of the memory cells using at least one of the estimated first and second numbers of errors.

Abstract: A controller includes an interface and storage circuitry. The interface communicates with a memory that includes memory cells that store data in multiple programming levels, and that are organized in Word Lines (WLs). Each WL connects to one or more cell-groups of the memory cells. The memory cells in some cell-groups suffer from an impairment that has a different severity for reading data units of different bit-significance values. The storage circuitry assigns multiple parity groups to data units stored in cell-groups belonging to consecutive WLs, so that a same parity group is assigned to data units of different bit-significance values in neighboring groups of Nwl consecutive WLs. Upon detecting a failure to access a data unit of a given parity group, due to the impairment, the storage circuitry recovers the data unit using other data units assigned to the given parity group, and that are stored in other cell-groups.

Abstract: A storage device includes circuitry and memory cells that store data in Np programming levels of threshold voltage values. The circuitry defines NRv threshold-sets, each includes Ns read thresholds that define Ns+1 zones, produces Ns readouts by reading, from a target WL, using the NS read thresholds, a target page that was stored encoded using an Error Correction Code (ECC), and produces a reference readout by reading the target page using optimal read thresholds. The circuitry identifies Np programming levels of memory cells in a neighbor WL for classifying target cells in the target WL into Np·NRv cell-groups. The circuitry calculates, per zone, Np LLR values, for the respective Np programming levels, based on the reference readout, the Ns readouts and the classification, assigns the LLR values to the target cells, and recovers the target page by applying to the assigned LLR values soft decoding for decoding the ECC.

Abstract: A controller includes an interface and storage circuitry. The interface communicates with a memory that includes memory cells that store data in multiple programming levels, and that are organized in Word Lines (WLs). Each WL connects to one or more cell-groups of the memory cells. The memory cells in some cell-groups suffer from an impairment that has a different severity for reading data units of different bit-significance values. The storage circuitry assigns multiple parity groups to data units stored in cell-groups belonging to consecutive WLs, so that a same parity group is assigned to data units of different bit-significance values in neighboring groups of Nwl consecutive WLs. Upon detecting a failure to access a data unit of a given parity group, due to the impairment, the storage circuitry recovers the data unit using other data units assigned to the given parity group, and that are stored in other cell-groups.

Abstract: A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.

Abstract: A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.

Abstract: A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.