Abstract: A phase detection apparatus is described for use in a phase lock loop (PLL). The apparatus has a first input for a reference signal, a second input for a loop feedback signal and an output for the phase difference signal. Two D-type flips flops are provided, the first being clocked with the reference signal and the second with the loop feedback signal. The output of the second flip-flop is delayed relative to the first flip-flop, thereby effecting minimal overlap, when using the phase detection apparatus in a fractional- N phase lock loop, of the interpolator activity with that of the charge pump.

Abstract: A differential charge pump PLL synthesizer with adjustable tuning voltage range including a voltage controlled oscillator responsive to a tuning voltage to provide an output frequency. A phase detector circuit is responsive to a reference frequency and the sub-multiple of the output frequency for generating up and down pulses. A differential charge pump is responsive to the up and down pulses for generating positive and negative differential current pulses. A loop filter is responsive to the positive and negative differential current pulses for providing a differential voltage. A differential amplifier circuit is responsive to the differential voltage and a shift voltage applied at a voltage terminal for shifting the output voltage range of the differential amplifier circuit to provide a predetermined tuning voltage range.