Abstract: A reconfigurable signal processing device that includes a plurality of programmable modules that are reconfigurable to perform one of a plurality of selected signal processing functions. The modules may be reconfigured under software control to act as one of a time base generator, a counter, an accumulator, an address register, a delay circuit, and a timer. The plurality of modules are selectively reconfigured and selectably interconnected by a configuration and control circuit that receives command signals from the host processor containing the control software. The device further includes a plurality of input channels for receiving and initially processing analog signals to be tested and a high speed memory for storing data as required for the selected signal processing device. The devices that can be formed by configuring and interconnecting the programmable modules are for example, a counter/timer, an arbitrary function generator, a pluse generator, and a digitizer.

Abstract: A system is described for locating faulty integrated circuits on a printed circuit card under the guidance of computer programmed in accordance with the circuit being tested. The disclosed system includes a current pulsing network allowing digital selection, as by the computer, of reference voltage levels at which current is injected into the circuit being tested.

Abstract: A probe is connected to a tri-state circuit which generates a programmable dc voltage to be impressed on a circuit node by the probed tip. Memory is provided for storing any change in tip voltage signifying a fault in the tri-state test. A separate circuit detects programmable data levels to eliminate gray area ambiguities. Further, a quick-check circuit determines whether a node is short circuited by determining whether toggling can occur at a node.

Abstract: A pair of comparators is provided with attenuated input signals. Each comparator is provided with a different reference level so that two sets of complementary digital outputs may be obtained with different pulse widths. Hysteresis control is provided to the comparators to compensate for noise present at the comparator inputs.

Abstract: A testing circuit is capable of testing digital circuits, such as gates, in logic 1, logic 0 and Hi-Z conditions. To accomplish this end two comparators are connected to the output of the digital circuit undergoing test while second inputs of both comparators are respectively connected to different reference voltages. By comparing the voltage level at the output of the digital circuit undergoing test with programmable reference voltages, unique truth tables are established for an operative digital circuit undergoing test.